opcodes/
authorAdam Nemet <anemet@caviumnetworks.com>
Wed, 18 Feb 2009 20:51:59 +0000 (20:51 +0000)
committerAdam Nemet <anemet@caviumnetworks.com>
Wed, 18 Feb 2009 20:51:59 +0000 (20:51 +0000)
* mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific
dmfc2 and dmtc2 before the architecture-level variants.

gas/testsuite/
* gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2.
* gas/mips/octeon.d: Update.
* gas/mips/octeon-ill.l: Update error message.

gas/testsuite/ChangeLog
gas/testsuite/gas/mips/octeon-ill.l
gas/testsuite/gas/mips/octeon.d
gas/testsuite/gas/mips/octeon.s
opcodes/ChangeLog
opcodes/mips-opc.c

index 5c0b5509cc6a0f52428c045ba4ef64c93191cfa6..18305c6ccf9bbdaed00e96832a81252427fd9ff3 100644 (file)
@@ -1,3 +1,9 @@
+2009-02-18  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2.
+       * gas/mips/octeon.d: Update.
+       * gas/mips/octeon-ill.l: Update error message.
+
 2009-02-16  Nick Clifton  <nickc@redhat.com>
 
        * gas/mips/e32-rel2.d: Adjust expected output to remove the 0x4000
index b90eaf17e1a18565c33c1c38e74d17693f2c3935..cdd1e5a8e236e382809dea94a786b8f41804dc34 100644 (file)
 .*:41: Error: opcode not supported on this processor.*
 .*:42: Error: opcode not supported on this processor.*
 .*:43: Error: opcode not supported on this processor.*
-.*:45: Error: expression out of range
-.*:46: Error: expression out of range
-.*:47: Error: register value used as expression
+.*:45: Error: illegal operands `dmfc2 \$2,0x10000'
+.*:46: Error: illegal operands `dmtc2 \$2,0x12345'
+.*:47: Error: illegal operands `dmfc2 \$9,\$12'
 .*:48: Error: illegal operands `dmfc2 \$4,\$15,4'
-.*:49: Error: register value used as expression
+.*:49: Error: illegal operands `dmtc2 \$16,\$8'
 .*:50: Error: illegal operands `dmtc2 \$22,\$7,\$4'
 .*:52: Error: Improper size \(32\)
 .*:54: Error: Improper position \(32\)
index 5e32ae6e5302167ba88a50abb7f338be6372e335..79b4001440752f312dd1e4aaaa9ffbd3919ad99b 100644 (file)
@@ -46,7 +46,11 @@ Disassembly of section .text:
 .*:    41606000        di
 .*:    41606020        ei
 .*:    48230084        dmfc2   \$3,0x84
+.*:    48260800        dmfc2   \$6,0x800
+.*:    482c0001        dmfc2   \$12,0x1
 .*:    48a84200        dmtc2   \$8,0x4200
+.*:    48a72000        dmtc2   \$7,0x2000
+.*:    48a20004        dmtc2   \$2,0x4
 .*:    73400008        mtm0    \$26
 .*:    7260000c        mtm1    \$19
 .*:    7240000d        mtm2    \$18
index 4772b4c9604d4104d835237ee3312c6d0dbf7657..c73ffd9a5a16d64fe538d8da1ef1448f11911b88 100644 (file)
@@ -47,7 +47,11 @@ foo:
         di
         ei
         dmfc2   $3,0x84
+        dmfc2   $6,0x800
+        dmfc2   $12,0x1
         dmtc2   $8,0x4200
+        dmtc2   $7,0x2000
+        dmtc2   $2,0x4
 
         mtm0    $26
         mtm1    $19
index 941aff1ac654265d50509bbc15a74d6a7560e194..db66f45e604bb13d8865cdaae556550e3aa10de5 100644 (file)
@@ -1,3 +1,8 @@
+2009-02-18  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific
+       dmfc2 and dmtc2 before the architecture-level variants.
+
 2009-02-18  Pierre Muller  <muller@ics.u-strasbg.fr>
 
        * fr30-opc.c: Regenerate.
index 12a8cbebff01c7f34f8c25053bb6f9aa079c1d2f..fdf90ae873fbdcbe0406f65b09ff22e73b1098ba 100644 (file)
@@ -1506,12 +1506,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc2tl",   "N,p",     0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
 {"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
 {"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
+{"dmfc2",   "t,i",     0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,              IOCT    },
 {"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
 {"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
-{"dmfc2",   "t,i",     0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,              IOCT    },
+{"dmtc2",   "t,i",     0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              IOCT    },
 {"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
 {"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
-{"dmtc2",   "t,i",     0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              IOCT    },
 {"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
 {"mfc2",    "t,G,H",   0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
 {"mfhc2",   "t,G",     0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },