2008-03-09 Paul Brook <paul@codesourcery.com>

	bfd/
	* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new
	Tag_VFP_arch values.

	binutils/
	* readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16".

	gas/
	* config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
	(parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
	(arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
	(aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
	* doc/c-arm.texi: Document new ARM FPU variants.

	gas/testsuite/
	* gas/arm/vfpv3-d16-bad.d: New test.
	* gas/arm/vfpv3-d16-bad.l: New test.

	include/opcode/
	* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 9027887700252e5f264fd4e259d2b32cc5ecec3f..a786a3e50e23363c9846370118e7bf024f59f2c6 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2008-03-09  Paul Brook  <paul@codesourcery.com>
+
+       * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new
+       Tag_VFP_arch values.
+
 2008-03-08  Paul Brook  <paul@codesourcery.com>
 
        * elf32-arm.c (insert_thumb_branch): Rewrite.

diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 6764e67b17edcc5aa40a7010c5b9dc7afe49ee81..1be33466560d09fccada929e654ad9d409935651 100644 (file)
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -6902,6 +6902,8 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
   /* Some tags have 0 = don't care, 1 = strong requirement,
      2 = weak requirement.  */
   static const int order_312[3] = {3, 1, 2};
+  /* For use with Tag_VFP_arch.  */
+  static const int order_01243[5] = {0, 1, 2, 4, 3};
   int i;
 
   if (!elf_known_obj_attributes_proc (obfd)[0].i)
@@ -6956,7 +6958,6 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
        case Tag_CPU_arch:
        case Tag_ARM_ISA_use:
        case Tag_THUMB_ISA_use:
-       case Tag_VFP_arch:
        case Tag_WMMX_arch:
        case Tag_NEON_arch:
          /* ??? Do NEON and WMMX conflict?  */
@@ -6984,6 +6985,11 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
          if (in_attr[i].i)
            out_attr[i].i = in_attr[i].i;
          break;
+       case Tag_VFP_arch:
+         if (in_attr[i].i > 4 || out_attr[i].i > 4
+             || order_01243[in_attr[i].i] > order_01243[out_attr[i].i])
+           out_attr[i].i = in_attr[i].i;
+         break;
        case Tag_PCS_config:
          if (out_attr[i].i == 0)
            out_attr[i].i = in_attr[i].i;

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 8aca5f1f1ad3d734029c4e0b962d4423b52ffbb9..946a010506c85373474f52de2ae65fd75cac1bd8 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2008-03-09  Paul Brook  <paul@codesourcery.com>
+
+       * readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16".
+
 2008-03-03  James E. Wilson  <wilson@tuliptree.org>
 
        * MAINTAINERS: Update my email address.

diff --git a/binutils/readelf.c b/binutils/readelf.c
index bcad624c712c681f44107fc12f1ac7e193233704..61c085ff8b67b6fc5c28737dd4c68ea4c0a36fd5 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -8628,8 +8628,8 @@ static const char *arm_attr_tag_CPU_arch[] =
 static const char *arm_attr_tag_ARM_ISA_use[] = {"No", "Yes"};
 static const char *arm_attr_tag_THUMB_ISA_use[] =
   {"No", "Thumb-1", "Thumb-2"};
-/* FIXME: VFPv3 encoding was extrapolated!  */
-static const char *arm_attr_tag_VFP_arch[] = {"No", "VFPv1", "VFPv2", "VFPv3"};
+static const char *arm_attr_tag_VFP_arch[] =
+  {"No", "VFPv1", "VFPv2", "VFPv3", "VFPv3-D16"};
 static const char *arm_attr_tag_WMMX_arch[] = {"No", "WMMXv1"};
 static const char *arm_attr_tag_NEON_arch[] = {"No", "NEONv1"};
 static const char *arm_attr_tag_ABI_PCS_config[] =

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b360a4b00addd575159b685d2c8461f002a6833e..8509e1c988ca5a8533286c882ef133fcd3b72ad3 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2008-03-09  Paul Brook  <paul@codesourcery.com>
+
+       * config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
+       (parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
+       (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
+       (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
+       * doc/c-arm.texi: Document new ARM FPU variants.
+
 2008-03-07  Paul Brook  <paul@codesourcery.com>
 
        * config/tc-arm.c (md_apply_fix): Use correct offset range.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 161b644ccbe65539fbcad55736f127811c0425f5..59a1d77d552d69844c409b27779da29b6bff9f0c 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -221,6 +221,8 @@ static const arm_feature_set fpu_vfp_ext_v1xd =
 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
+static const arm_feature_set fpu_vfp_ext_d32 =
+  ARM_FEATURE (0, FPU_VFP_EXT_D32);
 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
   ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
@@ -1607,16 +1609,16 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
 
   if (etype != REGLIST_VFP_S)
     {
-      /* VFPv3 allows 32 D registers.  */
-      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
+      /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant.  */
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
         {
           max_regs = 32;
           if (thumb_mode)
             ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
-                                    fpu_vfp_ext_v3);
+                                    fpu_vfp_ext_d32);
           else
             ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
-                                    fpu_vfp_ext_v3);
+                                    fpu_vfp_ext_d32);
         }
       else
         max_regs = 16;
@@ -6161,14 +6163,14 @@ encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
   if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
       && reg > 15)
     {
-      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
         {
           if (thumb_mode)
             ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
-                                    fpu_vfp_ext_v3);
+                                    fpu_vfp_ext_d32);
           else
             ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
-                                    fpu_vfp_ext_v3);
+                                    fpu_vfp_ext_d32);
         }
       else
         {
@@ -20211,10 +20213,13 @@ static const struct arm_option_cpu_value_table arm_fpus[] =
   {"softvfp+vfp",      FPU_ARCH_VFP_V2},
   {"vfp",              FPU_ARCH_VFP_V2},
   {"vfp9",             FPU_ARCH_VFP_V2},
-  {"vfp3",              FPU_ARCH_VFP_V3},
+  {"vfp3",              FPU_ARCH_VFP_V3}, /* For backwards compatbility.  */
   {"vfp10",            FPU_ARCH_VFP_V2},
   {"vfp10-r0",         FPU_ARCH_VFP_V1},
   {"vfpxd",            FPU_ARCH_VFP_V1xD},
+  {"vfpv2",            FPU_ARCH_VFP_V2},
+  {"vfpv3",            FPU_ARCH_VFP_V3},
+  {"vfpv3-d16",                FPU_ARCH_VFP_V3D16},
   {"arm1020t",         FPU_ARCH_VFP_V1},
   {"arm1020e",         FPU_ARCH_VFP_V2},
   {"arm1136jfs",       FPU_ARCH_VFP_V2},
@@ -20675,7 +20680,10 @@ aeabi_set_public_attributes (void)
     bfd_elf_add_proc_attr_int (stdoutput, 9,
        ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
   /* Tag_VFP_arch.  */
-  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
+  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_d32)
+      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_d32))
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 4);
+  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))
     bfd_elf_add_proc_attr_int (stdoutput, 10, 3);
   else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index ef5dcc09ce7e5e0009d3a02cb2c5be938b7bb1bb..2ee29328a87fc62de46b619ad4e28280b8fbbf9a 100644 (file)
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -190,11 +190,15 @@ The following format options are recognized:
 @code{vfp10-r0},
 @code{vfp9},
 @code{vfpxd},
+@code{vfpv2}
+@code{vfpv3}
+@code{vfpv3-d16}
 @code{arm1020t},
 @code{arm1020e},
-@code{arm1136jf-s}
+@code{arm1136jf-s},
+@code{maverick}
 and
-@code{maverick}.
+@code{neon}.
 
 In addition to determining which instructions are assembled, this option
 also affects the way in which the @code{.double} assembler directive behaves

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 939b9f7b73959fdc6c71b9630065551d9587094e..8ebab2e651db8d2c3d32fb29c6964873a41e050e 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2008-03-09  Paul Brook  <paul@codesourcery.com>
+
+       * gas/arm/vfpv3-d16-bad.d: New test.
+       * gas/arm/vfpv3-d16-bad.l: New test.
+
 2008-03-06  Andreas Krebbel  <krebbel1@de.ibm.com>
 
        * gas/s390/esa-g5.d (cdfbr, cdfr, cefbr, cefr, cxfbr, cxfr,

diff --git a/gas/testsuite/gas/arm/vfpv3-d16-bad.d b/gas/testsuite/gas/arm/vfpv3-d16-bad.d
new file mode 100644 (file)
index 0000000..0e26c7c
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfpv3-d16-bad.d
@@ -0,0 +1,4 @@
+# name: VFPv3-D16
+# as: -mfpu=vfpv3-d16
+# error-output: vfpv3-d16-bad.l
+# source: vfpv3-32drs.s

diff --git a/gas/testsuite/gas/arm/vfpv3-d16-bad.l b/gas/testsuite/gas/arm/vfpv3-d16-bad.l
new file mode 100644 (file)
index 0000000..1871d20
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfpv3-d16-bad.l
@@ -0,0 +1,53 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcpyd d3,d22'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcpyd d22,d3'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcvtds d22,s22'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcvtsd s22,d22'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmdhr d21,r4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmdlr d27,r5'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmrdh r6,d23'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmrdl r7,d25'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsitod d22,s22'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fuitod d21,s21'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `ftosid s20,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `ftosizd s20,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `ftouid s19,d19'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `ftouizd s19,d19'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fldd d19,\[r10,#4\]'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fstd d21,\[r10,#4\]'
+[^:]*:[0-9]+: Error: register out of range in list -- `fldmiad r10!,\{d18,d19,d20\}'
+[^:]*:[0-9]+: Error: register out of range in list -- `fldmiax r10!,\{d18,d19,d20\}'
+[^:]*:[0-9]+: Error: register out of range in list -- `fldmdbx r10!,\{d18,d19\}'
+[^:]*:[0-9]+: Error: register out of range in list -- `fstmiad r9,\{d20,d21,d22,d23,d24\}'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fabsd d12,d18'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fabsd d18,d19'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnegd d12,d18'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnegd d18,d19'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsqrtd d12,d18'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsqrtd d18,d19'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `faddd d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `faddd d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsubd d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsubd d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmuld d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmuld d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fdivd d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fdivd d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmacd d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmacd d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmscd d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmscd d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmuld d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmuld d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmacd d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmacd d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmscd d12,d18,d4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmscd d18,d19,d20'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmpd d3,d18'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmpd d18,d3'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmpzd d19'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmped d3,d18'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmped d18,d3'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmpezd d19'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmdrr d31,r3,r4'
+[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmrrd r5,r6,d30'

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 8b440720095aad078cdeaa05d05624d118d1ed74..919f2059dd26fc005363e2034679a72813f91734 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2008-03-09  Paul Brook  <paul@codesourcery.com>
+
+       * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
+
 2008-03-04  Paul Brook  <paul@codesourcery.com>
 
        * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.

diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 5f93fd76368babead78ba6b25517534b71702b5c..11cab3e8448581b1c5e045f53e059206e4f556cf 100644 (file)
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -64,6 +64,7 @@
 #define FPU_VFP_EXT_V2  0x02000000     /* ARM10E VFPr1.              */
 #define FPU_VFP_EXT_V3  0x01000000     /* VFPv3 insns.               */
 #define FPU_NEON_EXT_V1         0x00800000     /* Neon (SIMD) insns.         */
+#define FPU_VFP_EXT_D32  0x00400000    /* Registers D16-D31.         */
 
 /* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
    defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@@ -118,9 +119,10 @@
 #define FPU_VFP_V1xD   (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
 #define FPU_VFP_V1     (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
 #define FPU_VFP_V2     (FPU_VFP_V1 | FPU_VFP_EXT_V2)
-#define FPU_VFP_V3     (FPU_VFP_V2 | FPU_VFP_EXT_V3)
+#define FPU_VFP_V3D16  (FPU_VFP_V2 | FPU_VFP_EXT_V3)
+#define FPU_VFP_V3     (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
 #define FPU_VFP_HARD   (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
-                         | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1)
+                         | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
 #define FPU_FPA                (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
 
 /* Deprecated */
@@ -132,6 +134,7 @@
 #define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
 #define FPU_ARCH_VFP_V1          ARM_FEATURE (0, FPU_VFP_V1)
 #define FPU_ARCH_VFP_V2          ARM_FEATURE (0, FPU_VFP_V2)
+#define FPU_ARCH_VFP_V3D16     ARM_FEATURE (0, FPU_VFP_V3D16)
 #define FPU_ARCH_VFP_V3          ARM_FEATURE (0, FPU_VFP_V3)
 #define FPU_ARCH_NEON_V1  ARM_FEATURE (0, FPU_NEON_EXT_V1)
 #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \