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diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 732e38d3faf842bd68b7507228c6ff070ac5c9ba..2c160cdc9fb04f34bb795a11f6607a16512a91ce 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -63,6 +63,11 @@ Pages being developed and examples
 * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
 * [[sv/byteswap]]
+* Twin targetted instructions (two registers out, one implicit)
+  Explanation of the rules for twin register targets
+  (implicit RS, FRS) explained in SVP4 [[sv/svp64/appendix]]
+  - [[isa/svfixedarith]]
+  - [[isa/svfparith]]
 * TODO: OpenPOWER [[openpower/transcendentals]]
 
 Additional links: