mips.md (*mov<mode>_ra): Name previously unnamed MIPS16 $31 store insns.

	* config/mips/mips.md (*mov<mode>_ra): Name previously unnamed MIPS16
	$31 store insns.  Redefine using :GPR.

From-SVN: r86417

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3f089d55bebc4f338fdf0bf1bd238c2fa39df66a..7beb5cb8577eb1f4bd8c11d9ceea9617dcb1e488 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2004-08-23  Richard Sandiford  <rsandifo@redhat.com>
+
+       * config/mips/mips.md (*mov<mode>_ra): Name previously unnamed MIPS16
+       $31 store insns.  Redefine using :GPR.
+
 2004-08-23  Richard Sandiford  <rsandifo@redhat.com>
 
        * config/mips/mips.md (P): New mode macro.

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 781eafe62b2ea406b0c85c5b2e594d8620f682fb..fa7ee20561be212914c9e3261b18adecac57339d 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3432,13 +3432,13 @@ beq\t%2,%.,1b\;\
 ;; memory, since we don't have a constraint to match $31.  This
 ;; instruction can be generated by save_restore_insns.
 
-(define_insn ""
-  [(set (match_operand:DI 0 "stack_operand" "=m")
-       (reg:DI 31))]
-  "TARGET_MIPS16 && TARGET_64BIT"
-  "sd\t$31,%0"
-  [(set_attr "type"    "store")
-   (set_attr "mode"    "DI")])
+(define_insn "*mov<mode>_ra"
+  [(set (match_operand:GPR 0 "stack_operand" "=m")
+       (reg:GPR 31))]
+  "TARGET_MIPS16"
+  "<store>\t$31,%0"
+  [(set_attr "type" "store")
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "*movdi_32bit"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*x,*d,*B*C*D,*B*C*D,*d,*m")
@@ -3555,16 +3555,6 @@ beq\t%2,%.,1b\;\
     DONE;
 })
 
-;; We can only store $ra directly into a small sp offset.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "stack_operand" "=m")
-       (reg:SI 31))]
-  "TARGET_MIPS16"
-  "sw\t$31,%0"
-  [(set_attr "type"    "store")
-   (set_attr "mode"    "SI")])
-
 ;; The difference between these two is whether or not ints are allowed
 ;; in FP registers (off by default, use -mdebugh to enable).