opcodes: Correct address for ARC's "isa_config" aux reg

This patch changes the address for "isa_config" auxiliary register
from 0xC2 to the correct value 0xC1.  Moreover, it only exists in
arc700+ and not all ARCs.

opcodes/ChangeLog:

	* arc-regs.h: Change isa_config address to 0xc1.
	isa_config exists for ARC700 and ARCV2 and not ARCALL.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5bddae5c626a4dba5ca07ff3e9334ee39bcdd913..8dab47fcbb2cbfe3d6d7ee377184286ad21c14d8 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2022-11-22  Shahab Vahedi  <shahab@synopsys.com>
+
+       * arc-regs.h: Change isa_config address to 0xc1.
+       isa_config exists for ARC700 and ARCV2 and not ARCALL.
+
 2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
 
        * rx-decode.opc: Switch arguments of the MVTACGU insn.

diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h
index 2f296639442d8ee2890cedb377a7f21a4260966b..aa6b40de1f19a40c9ab6d3ae9359e679646c4564 100644 (file)
--- a/opcodes/arc-regs.h
+++ b/opcodes/arc-regs.h
@@ -207,7 +207,8 @@ DEF (0xac,  ARC_OPCODE_ARCALL,  NONE, se_dbg_data3)
 DEF (0xad,  ARC_OPCODE_ARCALL,  NONE, se_watch)
 DEF (0xc0,  ARC_OPCODE_ARCALL,  NONE, bpu_build)
 DEF (0xc1,  ARC_OPCODE_ARC600,  NONE, arc600_build_config)
-DEF (0xc2,  ARC_OPCODE_ARCALL,  NONE, isa_config)
+DEF (0xc1,  ARC_OPCODE_ARC700,  NONE, isa_config)
+DEF (0xc1,  ARC_OPCODE_ARCV2,   NONE, isa_config)
 DEF (0xf4,  ARC_OPCODE_ARCALL,  NONE, hwp_build)
 DEF (0xf5,  ARC_OPCODE_ARCALL,  NONE, pct_build)
 DEF (0xf6,  ARC_OPCODE_ARCALL,  NONE, cc_build)