r600g: use TGSI_PROPERTY to disable viewport and clipping
authorChristoph Bumiller <e0425955@student.tuwien.ac.at>
Fri, 16 May 2014 23:20:20 +0000 (01:20 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 2 Jun 2014 10:49:03 +0000 (12:49 +0200)
v2 get rid of magic value, use DEFINES
v3 update clip_disable together with vs_position_window_space

Big thanks to Marek Olšák!

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/evergreend.h
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/r600/r600_pipe.h
src/gallium/drivers/r600/r600_shader.c
src/gallium/drivers/r600/r600_shader.h
src/gallium/drivers/r600/r600_state.c
src/gallium/drivers/r600/r600_state_common.c
src/gallium/drivers/r600/r600d.h

index 5824fe0418ac0905cac31bd035e0ad4f50424a21..cd7fb1eeb6eafa643dbe62c5747bea7487c229be 100644 (file)
@@ -2285,7 +2285,6 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
        }
 
        r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
-       r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
        r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
 
        r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
@@ -2738,7 +2737,6 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
        }
 
        r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
-       r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
        r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
 
        r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
@@ -3072,6 +3070,17 @@ void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader
        r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
                               S_028860_NUM_GPRS(rshader->bc.ngpr) |
                               S_028860_STACK_SIZE(rshader->bc.nstack));
+       if (rshader->vs_position_window_space) {
+               r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
+                       S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
+       } else {
+               r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
+                       S_028818_VTX_W0_FMT(1) |
+                       S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
+                       S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
+                       S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
+
+       }
        r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
                               r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
        /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
index a17aff3108956d6925c0274f3667571c340870b4..8ea6aedb18a3eee50693879bc6c7815493f14d6d 100644 (file)
 #define R_028798_CB_BLEND6_CONTROL                   0x00028798
 #define R_02879C_CB_BLEND7_CONTROL                   0x0002879C
 #define R_028818_PA_CL_VTE_CNTL                      0x00028818
+#define   S_028818_VPORT_X_SCALE_ENA(x)                (((x) & 0x1) << 0)
+#define   G_028818_VPORT_X_SCALE_ENA(x)                (((x) >> 0 & 0x1)
+#define   C_028818_VPORT_X_SCALE_ENA                   0xFFFFFFFE
+#define   S_028818_VPORT_X_OFFSET_ENA(x)               (((x) & 0x1) << 1)
+#define   G_028818_VPORT_X_OFFSET_ENA(x)               (((x) >> 1 & 0x1)
+#define   C_028818_VPORT_X_OFFSET_ENA                  0xFFFFFFFD
+#define   S_028818_VPORT_Y_SCALE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_028818_VPORT_Y_SCALE_ENA(x)                (((x) >> 2 & 0x1)
+#define   C_028818_VPORT_Y_SCALE_ENA                   0xFFFFFFFB
+#define   S_028818_VPORT_Y_OFFSET_ENA(x)               (((x) & 0x1) << 3)
+#define   G_028818_VPORT_Y_OFFSET_ENA(x)               (((x) >> 3 & 0x1)
+#define   C_028818_VPORT_Y_OFFSET_ENA                  0xFFFFFFF7
+#define   S_028818_VPORT_Z_SCALE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_028818_VPORT_Z_SCALE_ENA(x)                (((x) >> 4 & 0x1)
+#define   C_028818_VPORT_Z_SCALE_ENA                   0xFFFFFFEF
+#define   S_028818_VPORT_Z_OFFSET_ENA(x)               (((x) & 0x1) << 5)
+#define   G_028818_VPORT_Z_OFFSET_ENA(x)               (((x) >> 5 & 0x1)
+#define   C_028818_VPORT_Z_OFFSET_ENA                  0xFFFFFFDF
+#define   S_028818_VTX_XY_FMT(x)                       (((x) & 0x1) << 8)
+#define   G_028818_VTX_XY_FMT(x)                       (((x) >> 8) & 0x1)
+#define   C_028818_VTX_XY_FMT                          0xFFFFFEFF
+#define   S_028818_VTX_Z_FMT(x)                        (((x) & 0x1) << 9)
+#define   G_028818_VTX_Z_FMT(x)                        (((x) >> 9) & 0x1)
+#define   C_028818_VTX_Z_FMT                           0xFFFFFDFF
+#define   S_028818_VTX_W0_FMT(x)                       (((x) & 0x1) << 10)
+#define   G_028818_VTX_W0_FMT(x)                       (((x) >> 10) & 0x1)
+#define   C_028818_VTX_W0_FMT                          0xFFFFFBFF
+
 #define R_028820_PA_CL_NANINF_CNTL                   0x00028820
 #define R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1         0x00028838
 #define   S_028838_PS_GPRS(x)                          (((x) & 0x1F) << 0)
index f834a9de15e86a82371c9f54fdcf470c42aec42c..2b65056c9531ad43e7a577b2d337b3d2f2b1631a 100644 (file)
@@ -260,7 +260,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
        case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
-        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
+       case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
+       case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
                return 1;
 
        case PIPE_CAP_COMPUTE:
@@ -316,7 +317,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_QUERY_LOD:
        case PIPE_CAP_SAMPLE_SHADING:
        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
-       case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
                return 0;
 
        /* Stream output. */
index 41203597e7fbb4026c7e32969b41d2a61608fa40..4585ace155e5f55f0ce86d310a920ed43c0c43a3 100644 (file)
@@ -108,6 +108,7 @@ struct r600_clip_misc_state {
        unsigned pa_cl_vs_out_cntl; /* from vertex shader */
        unsigned clip_plane_enable; /* from rasterizer    */
        unsigned clip_dist_write;   /* from vertex shader */
+       boolean clip_disable;       /* from vertex shader */
 };
 
 struct r600_alphatest_state {
index a4ed796b76874ebb32037ba126ffe495dc9bf4a1..b3d1998b98e6239df94d0849da45f8587e05df9c 100644 (file)
@@ -1708,6 +1708,10 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
                                if (property->u[0].Data == 1)
                                        shader->fs_write_all = TRUE;
                                break;
+                       case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
+                               if (property->u[0].Data == 1)
+                                       shader->vs_position_window_space = TRUE;
+                               break;
                        case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
                                /* we don't need this one */
                                break;
index ab9f1f02736565ac64f80f560150c35c1c87ccca..d6db8f063ac310452c1a6933f9d972c25471147c 100644 (file)
@@ -59,6 +59,7 @@ struct r600_shader {
        unsigned                nr_ps_color_exports;
        /* bit n is set if the shader writes gl_ClipDistance[n] */
        unsigned                clip_dist_write;
+       boolean                 vs_position_window_space;
        /* flag is set if the shader writes VS_OUT_MISC_VEC (e.g. for PSIZE) */
        boolean                 vs_out_misc_write;
        boolean                 vs_out_point_size;
index 31d7bd045192318829fff3096eaf1b6d3b23ce87..9e7a8e95289267fe973c002837e0e4877cf3d869 100644 (file)
@@ -2375,8 +2375,6 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
                r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
        }
 
-       r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
-
        r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
        r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
 
@@ -2588,6 +2586,17 @@ void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha
        r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
                               S_028868_NUM_GPRS(rshader->bc.ngpr) |
                               S_028868_STACK_SIZE(rshader->bc.nstack));
+       if (rshader->vs_position_window_space) {
+               r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
+                       S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
+       } else {
+               r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
+                       S_028818_VTX_W0_FMT(1) |
+                       S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
+                       S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
+                       S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
+
+       }
        r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
        /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
 
index dd3f7f8cc0c6fcb110bd954f507f39fcf69d33f8..8c37d0d2092bca2d2c0e361f7b89bc914f004004 100644 (file)
@@ -1178,9 +1178,11 @@ static bool r600_update_derived_state(struct r600_context *rctx)
                        update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
                        /* Update clip misc state. */
                        if (rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
-                                       rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
+                                       rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
+                                       rctx->clip_misc_state.clip_disable != rctx->gs_shader->current->shader.vs_position_window_space) {
                                rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl;
                                rctx->clip_misc_state.clip_dist_write = rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write;
+                               rctx->clip_misc_state.clip_disable = rctx->gs_shader->current->shader.vs_position_window_space;
                                rctx->clip_misc_state.atom.dirty = true;
                        }
                }
@@ -1210,9 +1212,11 @@ static bool r600_update_derived_state(struct r600_context *rctx)
 
                        /* Update clip misc state. */
                        if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
-                                       rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
+                                       rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
+                                       rctx->clip_misc_state.clip_disable != rctx->vs_shader->current->shader.vs_position_window_space) {
                                rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
                                rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
+                               rctx->clip_misc_state.clip_disable = rctx->vs_shader->current->shader.vs_position_window_space;
                                rctx->clip_misc_state.atom.dirty = true;
                        }
                }
@@ -1310,7 +1314,8 @@ void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom
 
        r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
                               state->pa_cl_clip_cntl |
-                              (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
+                              (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
+                               S_028810_CLIP_DISABLE(state->clip_disable));
        r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
                               state->pa_cl_vs_out_cntl |
                               (state->clip_plane_enable & state->clip_dist_write));
index bb8ca28bb504a3266c8b8b168180485c508f0569..8405fbbfa944596813adb0b5e8b0692b3a208614 100644 (file)
 #define   S_028818_VPORT_Z_OFFSET_ENA(x)               (((x) & 0x1) << 5)
 #define   G_028818_VPORT_Z_OFFSET_ENA(x)               (((x) >> 5 & 0x1)
 #define   C_028818_VPORT_Z_OFFSET_ENA                  0xFFFFFFDF
+#define   S_028818_VTX_XY_FMT(x)                       (((x) & 0x1) << 8)
+#define   G_028818_VTX_XY_FMT(x)                       (((x) >> 8) & 0x1)
+#define   C_028818_VTX_XY_FMT                          0xFFFFFEFF
+#define   S_028818_VTX_Z_FMT(x)                        (((x) & 0x1) << 9)
+#define   G_028818_VTX_Z_FMT(x)                        (((x) >> 9) & 0x1)
+#define   C_028818_VTX_Z_FMT                           0xFFFFFDFF
 #define   S_028818_VTX_W0_FMT(x)                       (((x) & 0x1) << 10)
 #define   G_028818_VTX_W0_FMT(x)                       (((x) >> 10) & 0x1)
 #define   C_028818_VTX_W0_FMT                          0xFFFFFBFF