whitespace

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 6480051e8ad0d9aba2fd04e07c4f67bea4108a61..433025c65c3de1b9eae08952be0e504a5ad145ff 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -179,17 +179,17 @@ numbering everywhere because the ANSI c specification is inherently LSB0:
 Example Vector-looped add operation implementation when elwidths are 64-bit:
 
 ```
- # add RT, RA,RB using the "uint64_t" union member, "l"
- for i in range(VL):
-      int_regfile[RT].l[i] = int_regfile[RA].l[i] + int_regfile[RB].l[i]
+    # vector-add RT, RA,RB using the "uint64_t" union member, "l"
+    for i in range(VL):
+        int_regfile[RT].l[i] = int_regfile[RA].l[i] + int_regfile[RB].l[i]
 ```
 
 However if elwidth overrides are set to 16 for both source and destination:
 
 ```
- # add RT, RA, RB using the "uint64_t" union member "s"
- for i in range(VL):
-      int_regfile[RT].s[i] = int_regfile[RA].s[i] + int_regfile[RB].s[i]
+    # vector-add RT, RA, RB using the "uint64_t" union member "s"
+    for i in range(VL):
+        int_regfile[RT].s[i] = int_regfile[RA].s[i] + int_regfile[RB].s[i]
 ```
 
 Hardware Architectural note: to avoid a Read-Modify-Write at the register
@@ -208,10 +208,9 @@ Performance designs.
 
 ## Scalar Identity Behaviour
 
-SVP64 is designed so that when the prefix is all zeros, and
-VL=1, no effect or
-influence occurs (no augmentation) such that all standard Power ISA
-v3.0/v3 1 instructions covered by the prefix are "unaltered". This
+SVP64 is designed so that when the prefix is all zeros, and VL=1, no
+effect or influence occurs (no augmentation) such that all standard Power
+ISA v3.0/v3 1 instructions covered by the prefix are "unaltered". This
 is termed `scalar identity behaviour` (based on the mathematical
 definition for "identity", as in, "identity matrix" or better "identity
 transformation").