fold-vec-abs-int.c: Remove scan-assembler stanzas.

[testsuite]

2018-01-26  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-abs-int.c: Remove scan-assembler stanzas.
	* gcc.target/powerpc/fold-vec-abs-int-fwrap.c: Same.
	* gcc.target/powerpc/fold-vec-abs-int.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-int.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-int.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.c: Remove scan-assembler stanzas.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrap.c: Same.
	* gcc.target/powerpc/fold-vec-abs-longlong.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-short.c: Add xxspltib to valid instruction list.
	* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Same.

From-SVN: r257097

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fa0a167e2fd741a7cad38bc8a64d803898de915d..adf8c01a82e8eb043c46ce29fcad5e6ec0d53a10 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,26 @@
+2018-01-26  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+       * gcc.target/powerpc/fold-vec-abs-int.c: Remove scan-assembler stanzas.
+       * gcc.target/powerpc/fold-vec-abs-int-fwrap.c: Same.
+       * gcc.target/powerpc/fold-vec-abs-int.p7.c: New.
+       * gcc.target/powerpc/fold-vec-abs-int.p8.c: New.
+       * gcc.target/powerpc/fold-vec-abs-int.p9.c: New.
+       * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: New.
+       * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: New.
+       * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: New.
+       * gcc.target/powerpc/fold-vec-abs-longlong.c: Remove scan-assembler
+       stanzas.
+       * gcc.target/powerpc/fold-vec-abs-longlong-fwrap.c: Same.
+       * gcc.target/powerpc/fold-vec-abs-longlong.p7.c: New.
+       * gcc.target/powerpc/fold-vec-abs-longlong.p8.c: New.
+       * gcc.target/powerpc/fold-vec-abs-longlong.p9.c: New.
+       * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p7.c: New.
+       * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: New.
+       * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: New.
+       * gcc.target/powerpc/fold-vec-abs-short.c: Add xxspltib to valid
+       instruction list.
+       * gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Same.
+
 2018-01-26  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
        * gcc.target/powerpc/fold-vec-cmp-int.c: Delete.

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
index 34dead4e916f3e7e3661d8edc2c446a03324bc36..22eec38f25efc1f3023915f261954a289b2a8a8e 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
@@ -13,6 +13,4 @@ test1 (vector signed int x)
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-int-fwrapv.p*.c tests.  */

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c
new file mode 100644 (file)
index 0000000..739f1c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c
@@ -0,0 +1,20 @@
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power7 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power7 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c
new file mode 100644 (file)
index 0000000..8c284ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c
@@ -0,0 +1,20 @@
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power8 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power8 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c
new file mode 100644 (file)
index 0000000..cde86b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c
@@ -0,0 +1,19 @@
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power9 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power9 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegw" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
index 77d9ca5c26b1bd49675056a013929d7fe4e77d0b..4fb3fbe8664573826d9bfcde063dbd59ec764fbc 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
@@ -13,6 +13,4 @@ test1 (vector signed int x)
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+/* scan-assembler entries moved to fold-vec-abs-int.p*.c files. */

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c
new file mode 100644 (file)
index 0000000..81b0fc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c
@@ -0,0 +1,19 @@
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power7 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power7" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c
new file mode 100644 (file)
index 0000000..4e55e0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c
@@ -0,0 +1,20 @@
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power8 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c
new file mode 100644 (file)
index 0000000..6f2c686
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power9 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegw" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
index 934618b91b2481d5cd0cab6dbc27cfd5fb120423..6c3108c60c78b76551145f146a4d76eef1a81648 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
@@ -13,6 +13,5 @@ test3 (vector signed long long x)
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-longlong.p*.c.  */
+

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c
new file mode 100644 (file)
index 0000000..244c247
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c
@@ -0,0 +1,20 @@
+
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c
new file mode 100644 (file)
index 0000000..8f1545d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mpower9-vector -O2 -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegd" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
index 5b59d19346def79baa7ea7d64c4bba8a5bebb2ad..4f5148ed2374fd450be1b4fdd751d81422f52dd8 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
@@ -13,6 +13,4 @@ test3 (vector signed long long x)
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-longlong.p*.c . */

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c
new file mode 100644 (file)
index 0000000..4fa0b6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c
new file mode 100644 (file)
index 0000000..16906ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c
@@ -0,0 +1,17 @@
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mpower9-vector -O2 -mcpu=power9" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegd" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */