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diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 97bf4d4c35e4b176131cfbd4d5d5b14c4605ffa0..cd6d492ef5346698f321ca4cc54a072dd5c9e441 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -12,6 +12,7 @@ Links:
  out of scope for this document [[openpower/sv/3d_vector_ops]]
 * [[simple_v_extension/specification/bitmanip]] previous version,
   contains pseudocode for sof, sif, sbf
+* https://en.m.wikipedia.org/wiki/X86_Bit_manipulation_instruction_set#TBM_(Trailing_Bit_Manipulation)
 
 The core Power ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism.
 Therefore there are not that many cases where *actual* Vector