add elstrided/sea on ldst_idx mode

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index b3bae0d0283b2af2680ce74b0fa2321b6d333db1..6e86f61807c366a9d8278c90a4ca55276cae9e85 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1062,6 +1062,7 @@ class SVP64Asm:
         predresult = False
         failfirst = False
         ldst_elstride = 0
+        sea = False
 
         vli = False
         sea = False
@@ -1284,9 +1285,16 @@ class SVP64Asm:
                 svp64_rm.branch.sz = 1
 
         else:
+            ######################################
+            # "element-strided" mode, ldst_idx
+            if sv_mode == 0b01 and is_ldst_idx:
+                mode |= src_zero << SVP64MODE.SZ  # predicate zeroing
+                mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
+                mode |= sea << SVP64MODE.SEA  # el-strided
+
             ######################################
             # "normal" mode
-            if sv_mode is None:
+            elif sv_mode is None:
                 mode |= src_zero << SVP64MODE.SZ  # predicate zeroing
                 mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
                 if is_ldst:

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 6bcfcc844cd243a8dae9b2241da7a8e98b5e4444..dc146447dafcd64038a40ca5512e28f3334ba940 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -295,5 +295,13 @@ class SVSTATETestCase(unittest.TestCase):
         self._do_tst(expected)
 
 
+    def test_19_ldst_idx_els(self):
+        expected = [
+                    "sv.stdx/els *4,16,2",
+                    "sv.ldx/els *4,16,2",
+                        ]
+        self._do_tst(expected)
+
+
 if __name__ == "__main__":
     unittest.main()