X86: Hook in the M5 pseudo insts.

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index b8013165ee97dc5ceb03de3b86a973d47722597a..4ebe03d84fb7d76f4f78f9a02f33fddf04defacb 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -163,8 +163,96 @@
                 }
                 0x02: lar_Gv_Ew();
                 0x03: lsl_Gv_Ew();
-                //sandpile.org doesn't seem to know what this is... ?
-                0x04: loadall_or_reset_or_hang();
+                // sandpile.org doesn't seem to know what this is...? We'll
+                // use it for pseudo instructions. We've got 16 bits of space
+                // to play with so there can be quite a few pseudo
+                // instructions.
+                //0x04: loadall_or_reset_or_hang();
+                0x4: decode IMMEDIATE {
+                    format BasicOperate {
+#if FULL_SYSTEM
+                        0x00: m5arm({{
+                            PseudoInst::arm(xc->tcBase());
+                        }}, IsNonSpeculative);
+                        0x01: m5quiesce({{
+                            PseudoInst::quiesce(xc->tcBase());
+                        }}, IsNonSpeculative);
+                        0x02: m5quiesceNs({{
+                            PseudoInst::quiesceNs(xc->tcBase(), Rdi);
+                        }}, IsNonSpeculative);
+                        0x03: m5quiesceCycle({{
+                            PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
+                        }}, IsNonSpeculative);
+                        0x04: m5quiesceTime({{
+                            Rax = PseudoInst::quiesceTime(xc->tcBase());
+                        }}, IsNonSpeculative);
+#endif
+                        0x07: m5rpns({{
+                            Rax = PseudoInst::rpns(xc->tcBase());
+                        }}, IsNonSpeculative);
+                        0x21: m5exit({{
+                            PseudoInst::m5exit(xc->tcBase(), Rdi);
+                        }}, IsNonSpeculative);
+#if FULL_SYSTEM
+                        0x30: m5initparam({{
+                            Rax = xc->tcBase()->getCpuPtr()->
+                                      system->init_param;
+                        }}, IsNonSpeculative);
+                        0x31: m5loadsymbol({{
+                            PseudoInst::loadsymbol(xc->tcBase());
+                        }}, IsNonSpeculative);
+#endif
+                        0x40: m5resetstats({{
+                            PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+                        0x41: m5dumpstats({{
+                            PseudoInst::dumpstats(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+                        0x42: m5dumpresetstats({{
+                            PseudoInst::dumpresetstats(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+                        0x43: m5checkpoint({{
+                            PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+#if FULL_SYSTEM
+                        0x50: m5readfile({{
+                            Rax = PseudoInst::readfile(
+                                xc->tcBase(), Rdi, Rsi, Rdx);
+                        }}, IsNonSpeculative);
+#endif
+                        0x51: m5debugbreak({{
+                            PseudoInst::debugbreak(xc->tcBase());
+                        }}, IsNonSpeculative);
+                        0x52: m5switchcpu({{
+                            PseudoInst::switchcpu(xc->tcBase());
+                        }}, IsNonSpeculative);
+#if FULL_SYSTEM
+                        0x53: m5addsymbol({{
+                            PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+#endif
+                        0x54: m5panic({{
+                            panic("M5 panic instruction called at pc=%#x.\n",
+                                xc->readPC());
+                        }}, IsNonSpeculative);
+                        0x55: m5reserved1({{
+                            warn("M5 reserved opcode 1 ignored.\n");
+                        }}, IsNonSpeculative);
+                        0x56: m5reserved2({{
+                            warn("M5 reserved opcode 2 ignored.\n");
+                        }}, IsNonSpeculative);
+                        0x57: m5reserved3({{
+                            warn("M5 reserved opcode 3 ignored.\n");
+                        }}, IsNonSpeculative);
+                        0x58: m5reserved4({{
+                            warn("M5 reserved opcode 4 ignored.\n");
+                        }}, IsNonSpeculative);
+                        0x59: m5reserved5({{
+                            warn("M5 reserved opcode 5 ignored.\n");
+                        }}, IsNonSpeculative);
+                        default: Inst::UD2();
+                    }
+                }
 #if FULL_SYSTEM
                 0x05: syscall();
 #else

diff --git a/src/arch/x86/isa/formats/basic.isa b/src/arch/x86/isa/formats/basic.isa
index 7aea7085fdab01e5dd175a2afeb674261fb52aef..b96bae238f226e80c04a0ab2af6f9bf6e78062a0 100644 (file)
--- a/src/arch/x86/isa/formats/basic.isa
+++ b/src/arch/x86/isa/formats/basic.isa
@@ -147,3 +147,11 @@ def template BasicDecode {{
 def template BasicDecodeWithMnemonic {{
     return new %(class_name)s("%(mnemonic)s", machInst);
 }};
+
+def format BasicOperate(code, *flags) {{
+        iop = InstObjParams(name, Name, 'X86ISA::X86StaticInst', code, flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};

diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index cddc4247ce2a723d8cf50d935c98ef95b497d8a3..909f2f3896cb6b195af3ea128d72122468ef4a71 100644 (file)
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -156,6 +156,7 @@ output exec {{
 #include "sim/sim_exit.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
+#include "sim/pseudo_inst.hh"
 
 using namespace X86ISA;
 using namespace std;

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 343b37d413a02a5aff3cca2c78c29499a32ab6dc..a409d1f0f7b9995963f597e1373df28576347b3e 100644 (file)
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -113,6 +113,10 @@ def operands {{
         'Rbx':           ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13),
         'Rcx':           ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14),
         'Rdx':           ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15),
+        'Rsp':           ('IntReg', 'uqw', '(INTREG_RSP)', 'IsInteger', 16),
+        'Rbp':           ('IntReg', 'uqw', '(INTREG_RBP)', 'IsInteger', 17),
+        'Rsi':           ('IntReg', 'uqw', '(INTREG_RSI)', 'IsInteger', 18),
+        'Rdi':           ('IntReg', 'uqw', '(INTREG_RDI)', 'IsInteger', 19),
         'FpSrcReg1':     ('FloatReg', 'df', 'src1', 'IsFloating', 20),
         'FpSrcReg2':     ('FloatReg', 'df', 'src2', 'IsFloating', 21),
         'FpDestReg':     ('FloatReg', 'df', 'dest', 'IsFloating', 22),

diff --git a/src/arch/x86/predecoder_tables.cc b/src/arch/x86/predecoder_tables.cc
index bcd5face690ad0830a6c0884178649531117a31f..5f2b5c421eae15833afb1f5631d3cf7e84a2da70 100644 (file)
--- a/src/arch/x86/predecoder_tables.cc
+++ b/src/arch/x86/predecoder_tables.cc
@@ -201,7 +201,7 @@ namespace X86ISA
     //For two byte instructions
         {    //LSB
 //     MSB   0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
-/*      0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY ,
+/*      0 */ 0 , 0 , 0 , 0 , WO, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY ,
 /*      0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*      2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*      3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,