const struct pipe_draw_info *info = emit->info;
enum pc_di_primtype primtype = ctx->primtypes[info->mode];
- fd6_emit_state(ring, emit);
+ if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
+ struct fd_ringbuffer *state;
+
+ state = fd6_build_vbo_state(emit, emit->vs);
+ fd6_emit_add_group(emit, state, FD6_GROUP_VBO, 0x7);
+ fd_ringbuffer_del(state);
+ }
- if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
- fd6_emit_vertex_bufs(ring, emit);
+ fd6_emit_state(ring, emit);
OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
}
}
-void
-fd6_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd6_emit *emit)
+struct fd_ringbuffer *
+fd6_build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
{
- int32_t i, j;
const struct fd_vertex_state *vtx = emit->vtx;
- const struct ir3_shader_variant *vp = emit->vs;
+ int32_t i, j;
+
+ struct fd_ringbuffer *ring =
+ fd_ringbuffer_new_flags(emit->ctx->pipe, 4 * (10 * vp->inputs_count + 2),
+ FD_RINGBUFFER_OBJECT | FD_RINGBUFFER_STREAMING);
for (i = 0, j = 0; i <= vp->inputs_count; i++) {
if (vp->inputs[i].sysval)
OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
+
+ return ring;
}
static struct fd_ringbuffer *
FD6_GROUP_PROG,
FD6_GROUP_ZSA,
FD6_GROUP_ZSA_BINNING,
+ FD6_GROUP_VBO,
FD6_GROUP_VS_CONST,
FD6_GROUP_FS_CONST,
FD6_GROUP_VS_TEX,
enum a6xx_state_block sb, struct fd_texture_stateobj *tex,
unsigned bcolor_offset);
-void fd6_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd6_emit *emit);
+struct fd_ringbuffer * fd6_build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp);
void fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit);