Port: Align port names in C++ and Python

This patch is a first step to align the port names used in the Python
world and the C++ world. Ultimately it serves to make the use of
config.json together with output from the simulation easier, including
post-processing of statistics.

Most notably, the CPU, cache, and bus is addressed in this patch, and
there might be other ports that should be updated accordingly. The
dash name separator has also been replaced with a "." which is what is
used to concatenate the names in python, and a separation is made
between the master and slave port in the bus.

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 5803895641def70c717b8ba0d5565484fddf0535..f67691d0ade38b756d23a623b622e8556f854761 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -82,8 +82,9 @@ using namespace std;
 using namespace TheISA;
 using namespace ThePipeline;
 
-InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
-    CpuPort(_cacheUnit->name() + "-cache-port", _cacheUnit->cpu),
+InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit,
+                                 const std::string& name) :
+    CpuPort(_cacheUnit->name() + name, _cacheUnit->cpu),
     cacheUnit(_cacheUnit)
 { }
 
@@ -230,8 +231,8 @@ InOrderCPU::InOrderCPU(Params *params)
       stageWidth(params->stageWidth),
       resPool(new ResourcePool(this, params)),
       timeBuffer(2 , 2),
-      dataPort(resPool->getDataUnit()),
-      instPort(resPool->getInstUnit()),
+      dataPort(resPool->getDataUnit(), ".dcache_port"),
+      instPort(resPool->getInstUnit(), ".icache_port"),
       removeInstsThisCycle(false),
       activityRec(params->name, NumStages, 10, params->activity),
       system(params->system),

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 615d0eb90a24b289722120211bc8186be580fd1f..3103201dd909874f9ed7d5ed5b2c569191a132be 100644 (file)
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -165,7 +165,7 @@ class InOrderCPU : public BaseCPU
 
       public:
         /** Default constructor. */
-        CachePort(CacheUnit *_cacheUnit);
+        CachePort(CacheUnit *_cacheUnit, const std::string& name);
 
       protected:
 

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 41128110b822ffe41b347021db76ebf2d7be97fa..b1fd12a2ee014268bc3a3899400e1257d645d724 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -141,7 +141,7 @@ class FullO3CPU : public BaseO3CPU
       public:
         /** Default constructor. */
         IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
-            : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
+            : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
         { }
 
       protected:
@@ -168,7 +168,7 @@ class FullO3CPU : public BaseO3CPU
       public:
         /** Default constructor. */
         DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
-            : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
+            : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
         { }
 
       protected:

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 0886b276f7d52ac424e573267de0c863dac8e733..fc672493983ce1ef60340ad460fce07d5a539da4 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -105,7 +105,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
     : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
       simulate_data_stalls(p->simulate_data_stalls),
       simulate_inst_stalls(p->simulate_inst_stalls),
-      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
+      icachePort(name() + ".icache_port", this),
+      dcachePort(name() + ".dcache_port", this),
       fastmem(p->fastmem)
 {
     _status = Idle;

diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 95edea0b6713ca2a801ccd2ec98a5e2cd575fd19..b6b78c5db472976e4438184a0e5caad0ff48e791 100644 (file)
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -178,7 +178,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
       public:
 
         IcachePort(TimingSimpleCPU *_cpu)
-            : TimingCPUPort(_cpu->name() + "-iport", _cpu),
+            : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
               tickEvent(_cpu)
         { }
 
@@ -206,7 +206,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
       public:
 
         DcachePort(TimingSimpleCPU *_cpu)
-            : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)
+            : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
+              tickEvent(_cpu)
         { }
 
       protected:

diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 401f910acab03b3f56ebfe21ead8a0fc890f2d26..a50dd933e49b26d343a8078d0bb430b5db389a6a 100644 (file)
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -47,7 +47,7 @@
 #include "sim/system.hh"
 
 DmaPort::DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff)
-    : MasterPort(dev->name() + "-dma", dev), device(dev), sys(s),
+    : MasterPort(dev->name() + ".dma", dev), device(dev), sys(s),
       masterId(s->getMasterId(dev->name())),
       pendingCount(0), actionInProgress(0), drainEvent(NULL),
       backoffTime(0), minBackoffDelay(min_backoff),

diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index b03afc5c6b33b538ff0710c5c5bfc743f823a9d2..30779cfb47dd8a7674423ab59f7418337467a9b3 100644 (file)
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -47,7 +47,7 @@
 #include "sim/system.hh"
 
 PioPort::PioPort(PioDevice *dev)
-    : SimpleTimingPort(dev->name() + "-pio", dev), device(dev)
+    : SimpleTimingPort(dev->name() + ".pio", dev), device(dev)
 {
 }
 

diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 3a5313e7ba45ad93ff408a0750e9158e84c5c86f..e9dc68a030570b9ff18278fb1e7d2845a03d34d8 100644 (file)
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -79,9 +79,9 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string &_name,
 
 Bridge::Bridge(Params *p)
     : MemObject(p),
-      slavePort(p->name + "-slave", this, masterPort, p->delay,
+      slavePort(p->name + ".slave", this, masterPort, p->delay,
                 p->nack_delay, p->resp_size, p->ranges),
-      masterPort(p->name + "-master", this, slavePort, p->delay, p->req_size),
+      masterPort(p->name + ".master", this, slavePort, p->delay, p->req_size),
       ackWrites(p->write_ack), _params(p)
 {
     if (ackWrites)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index f7901261ff6f7e238ac3d649a21853b2d73d5f09..7b332e31d7800374d9f01e7b24ea2b57b54520f8 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -72,9 +72,9 @@ Cache<TagStore>::Cache(const Params *p, TagStore *tags)
     tempBlock = new BlkType();
     tempBlock->data = new uint8_t[blkSize];
 
-    cpuSidePort = new CpuSidePort(p->name + "-cpu_side_port", this,
+    cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this,
                                   "CpuSidePort");
-    memSidePort = new MemSidePort(p->name + "-mem_side_port", this,
+    memSidePort = new MemSidePort(p->name + ".mem_side", this,
                                   "MemSidePort");
 
     tags->setCache(this);

diff --git a/src/mem/coherent_bus.cc b/src/mem/coherent_bus.cc
index 5bcb2f14fd741fe6b566e3aa8fe1f28432864265..b0dedfaf47ed9fb7249d795335280870127fcf81 100644 (file)
--- a/src/mem/coherent_bus.cc
+++ b/src/mem/coherent_bus.cc
@@ -62,7 +62,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
     // vector ports, and the presence of the default port, the ports
     // are enumerated starting from zero
     for (int i = 0; i < p->port_master_connection_count; ++i) {
-        std::string portName = csprintf("%s-p%d", name(), i);
+        std::string portName = csprintf("%s.master[%d]", name(), i);
         MasterPort* bp = new CoherentBusMasterPort(portName, *this, i);
         masterPorts.push_back(bp);
     }
@@ -71,7 +71,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
     // our corresponding master port
     if (p->port_default_connection_count) {
         defaultPortID = masterPorts.size();
-        std::string portName = csprintf("%s-default", name());
+        std::string portName = name() + ".default";
         MasterPort* bp = new CoherentBusMasterPort(portName, *this,
                                                    defaultPortID);
         masterPorts.push_back(bp);
@@ -79,7 +79,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
 
     // create the slave ports, once again starting at zero
     for (int i = 0; i < p->port_slave_connection_count; ++i) {
-        std::string portName = csprintf("%s-p%d", name(), i);
+        std::string portName = csprintf("%s.slave[%d]", name(), i);
         SlavePort* bp = new CoherentBusSlavePort(portName, *this, i);
         slavePorts.push_back(bp);
     }

diff --git a/src/mem/noncoherent_bus.cc b/src/mem/noncoherent_bus.cc
index fb306bfebe090a37dfead1ce4c2163d2e3c8894a..237e8726b8d7dc6288c43b10a76f01dafad9a53d 100644 (file)
--- a/src/mem/noncoherent_bus.cc
+++ b/src/mem/noncoherent_bus.cc
@@ -62,7 +62,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
     // vector ports, and the presence of the default port, the ports
     // are enumerated starting from zero
     for (int i = 0; i < p->port_master_connection_count; ++i) {
-        std::string portName = csprintf("%s-p%d", name(), i);
+        std::string portName = csprintf("%s.master[%d]", name(), i);
         MasterPort* bp = new NoncoherentBusMasterPort(portName, *this, i);
         masterPorts.push_back(bp);
     }
@@ -71,7 +71,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
     // our corresponding master port
     if (p->port_default_connection_count) {
         defaultPortID = masterPorts.size();
-        std::string portName = csprintf("%s-default", name());
+        std::string portName = name() + ".default";
         MasterPort* bp = new NoncoherentBusMasterPort(portName, *this,
                                                       defaultPortID);
         masterPorts.push_back(bp);
@@ -79,7 +79,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
 
     // create the slave ports, once again starting at zero
     for (int i = 0; i < p->port_slave_connection_count; ++i) {
-        std::string portName = csprintf("%s-p%d", name(), i);
+        std::string portName = csprintf("%s.slave[%d]", name(), i);
         SlavePort* bp = new NoncoherentBusSlavePort(portName, *this, i);
         slavePorts.push_back(bp);
     }