aarch64: Fix an ICE in aarch64_short_vector_p [PR95459]

In aarch64_short_vector_p, we are simply checking whether a type (and a mode)
is a 64/128-bit short vector or not.  This should not be affected by the value
of TARGET_SVE.  Simply leave later code to report an error if SVE is disabled.

2020-06-02  Felix Yang  <felix.yang@huawei.com>

gcc/
	PR target/95459
	* config/aarch64/aarch64.c (aarch64_short_vector_p):
	Leave later code to report an error if SVE is disabled.

gcc/testsuite/
	PR target/95459
	* gcc.target/aarch64/mgeneral-regs_6.c: New test.

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 7feff77adf6b7f84b19dca7894323a116a2c0dc9..6352d4ff78ad183d5e7de86e62b267803347ddfe 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -16800,7 +16800,8 @@ aarch64_short_vector_p (const_tree type,
     {
       /* Rely only on the type, not the mode, when processing SVE types.  */
       if (type && aarch64_some_values_include_pst_objects_p (type))
-       gcc_assert (aarch64_sve_mode_p (mode));
+       /* Leave later code to report an error if SVE is disabled.  */
+       gcc_assert (!TARGET_SVE || aarch64_sve_mode_p (mode));
       else
        size = GET_MODE_SIZE (mode);
     }

diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c
new file mode 100644 (file)
index 0000000..427ae6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c
@@ -0,0 +1,15 @@
+/* { dg-options "-O2 -march=armv8.2-a+sve" } */
+/* { dg-prune-output "compilation terminated" } */
+
+#include <arm_sve.h>
+
+#pragma GCC push_options
+#pragma GCC target "general-regs-only"
+
+svint8x2_t
+foo (svint8_t x0, svint8_t x1) /* { dg-error {'foo' requires the SVE ISA extension} } */
+{
+  return svcreate2 (x0, x1); /* { dg-error {ACLE function 'svcreate2_s8' is incompatible with the use of '-mgeneral-regs-only'} } */
+}
+
+#pragma GCC pop_options