[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWER"
- "{fa|fadd} %0,%1,%2"
+ "TARGET_POWERPC"
+ "fadds %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC"
- "fadds %0,%1,%2"
+ "TARGET_POWER"
+ "{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")])
(define_expand "subsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWER"
- "{fs|fsub} %0,%1,%2"
+ "TARGET_POWERPC"
+ "fsubs %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC"
- "fsubs %0,%1,%2"
+ "TARGET_POWER"
+ "{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")])
(define_expand "mulsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWER"
- "{fm|fmul} %0,%1,%2"
+ "TARGET_POWERPC"
+ "fmuls %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC"
- "fmuls %0,%1,%2"
+ "TARGET_POWER"
+ "{fm|fmul} %0,%1,%2"
[(set_attr "type" "fp")])
(define_expand "divsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWER"
- "{fd|fdiv} %0,%1,%2"
+ "TARGET_POWERPC"
+ "fdivs %0,%1,%2"
[(set_attr "type" "sdiv")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC"
- "fdivs %0,%1,%2"
+ "TARGET_POWER"
+ "{fd|fdiv} %0,%1,%2"
[(set_attr "type" "sdiv")])
(define_insn ""
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))]
- "TARGET_POWER"
- "{fma|fmadd} %0,%1,%2,%3"
+ "TARGET_POWERPC"
+ "fmadds %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC"
- "fmadds %0,%1,%2,%3"
+ "TARGET_POWER"
+ "{fma|fmadd} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))]
- "TARGET_POWER"
- "{fms|fmsub} %0,%1,%2,%3"
+ "TARGET_POWERPC"
+ "fmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC"
- "fmsubs %0,%1,%2,%3"
+ "TARGET_POWER"
+ "{fms|fmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
- "TARGET_POWER"
- "{fnma|fnmadd} %0,%1,%2,%3"
+ "TARGET_POWERPC"
+ "fnmadds %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
- "TARGET_POWERPC"
- "fnmadds %0,%1,%2,%3"
+ "TARGET_POWER"
+ "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
- "TARGET_POWER"
- "{fnms|fnmsub} %0,%1,%2,%3"
+ "TARGET_POWERPC"
+ "fnmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
- "TARGET_POWERPC"
- "fnmsubs %0,%1,%2,%3"
+ "TARGET_POWER"
+ "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_expand "sqrtsf2"