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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
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--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -1,4 +1,4 @@
-# OPF ISA WG External RFC LS001 08Sep2022
+# OPF ISA WG External RFC LS001 v2 14Sep2022
 
 * RFC Author: Luke Kenneth Casson Leighton.
 * RFC Contributors/Ideas: Brad Frey, Paul Mackerras, Konstantinos Magritis,
@@ -65,6 +65,33 @@ capability present in every Commercial 3D GPU ISA, but it
 is the *Vectorised* Branch-Conditional that is augmented, not Scalar
 Branch.
 
+# Basic principle
+
+The basic principle of Simple-V is to provide a Precise-Interruptible
+Zero-Overhead register "offsetting" system which augments instructions, by
+incrementing the register numbering progressively *and automatically*
+each time round the "loop".  Thus it may be considered to be a form
+of "Sub-Program-Counter" and at its simplest level can replace a large
+sequence of regularly-increasing loop-unrolled instructions with just two:
+one to set the Vector length and one saying where to
+start from in the regfile.
+
+On this sound and profoundly simple concept which leverages *Scalar*
+Micro-architectural capabilities much more comprehensive festures are
+easy to add, working up towards an ISA that easily matches the capability
+of powerful 3D GPU Vector Supercomputing ISAs, without ever adding even
+one single Vector opcode.
+The inspiration for this came from the fact that on examination of every
+Vector ISA pseudocode encountered the Vector operations were expressed
+as a for-loop on a Scalar element
+operation, and then both a Scalar **and** a Vector instruction was added.
+
+It felt natural to separate the two at both the ISA and the Hardware Level
+and thus provide only Scalar instructions (instantly halving the number
+of instructions), leaving it up to implementors
+to implement Superscalar and Multi-Issue Micro-architectures at their
+discretion.
+
 # Extension Levels
 
 Simple-V has been subdivided into levels akin to the Power ISA Compliancy