arch-riscv: fixed read of {M,S,U}TVEC.

As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25648
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 2296992f28333a4dfd62dd6589b1be1017d759a8..2ef8df44b9c91464fba6c9771de20ea95186296d 100644 (file)
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -130,7 +130,7 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         tc->setMiscReg(MISCREG_STATUS, status);
 
         // Set PC to fault handler address
-        Addr addr = tc->readMiscReg(tvec) >> 2;
+        Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
         if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
             addr += 4 * _code;
         pcState.set(addr);