replace SATAX with sata_genx

diff --git a/README b/README
index ac5d06e5c5b8addf036878acea4c9e92113e58ea..9e45ea863b4f1b0bdc4bbf4d019d396e571902d0 100644 (file)
--- a/README
+++ b/README
@@ -10,7 +10,7 @@
 
 [> Intro
 -----------
-LiteSATA provides a small footprint and configurable SATA1/2/3 core.
+LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
 
 LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
 FPGA IP cores by providing simple, elegant and efficient implementations of

diff --git a/doc/source/docs/introducing_litesata/about_litesata.rst b/doc/source/docs/introducing_litesata/about_litesata.rst
index 30183161bec2266856ad162935b054f9af3d865a..28385021dbf6f4212c3075a2ad94c4a6ee55dfe5 100644 (file)
--- a/doc/source/docs/introducing_litesata/about_litesata.rst
+++ b/doc/source/docs/introducing_litesata/about_litesata.rst
@@ -4,7 +4,7 @@
 About LiteSATA
 ================
 
-LiteSATA provides a small footprint and configurable SATA1/2/3 core.
+LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
 
 LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
 FPGA IP cores by providing simple, elegant and efficient implementations of

diff --git a/doc/source/home_page_layout.html b/doc/source/home_page_layout.html
index 7e617df717b1adefeede6d229ed44d539ec2cc16..d0fa7c25289d6850f33e5c3ea92c2deaada18683 100644 (file)
--- a/doc/source/home_page_layout.html
+++ b/doc/source/home_page_layout.html
@@ -1,6 +1,6 @@
 <img alt="./_static/LiteSATA_logo_full.png" src="_static/LiteSATA_logo_full.png">
 
-<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA1/2/3 core</b>.</h3>
+<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2/3 core</b>.</h3>
 
 <div class="container" style="width:100%;margin-bottom:10px;">
 

diff --git a/litesata/common.py b/litesata/common.py
index d16536627b3f86abf17eeca8fc57650a66bc461e..2a7bca0c4cf68a9133f90d5656450a1cd9d16ced 100644 (file)
--- a/litesata/common.py
+++ b/litesata/common.py
@@ -13,13 +13,19 @@ from migen.flow.plumbing import Buffer
 from migen.actorlib.fifo import *
 from migen.actorlib.structuring import Pipeline, Converter
 
-# PHY / Link Layers
+bitrates = {
+       "sata_gen3"     :       6.0,
+       "sata_gen2"     :       3.0,
+       "sata_gen1"     :       1.5,
+}
+
 frequencies = {
-       "SATA3" :       150.0,
-       "SATA2" :       75.0,
-       "SATA1" :       37.5,
+       "sata_gen3"     :       150.0,
+       "sata_gen2"     :       75.0,
+       "sata_gen1"     :       37.5,
 }
 
+# PHY / Link Layers
 primitives = {
        "ALIGN" :       0x7B4A4ABC,
        "CONT"  :       0X9999AA7C,

diff --git a/litesata/phy/datapath.py b/litesata/phy/datapath.py
index 60f554428d9e93c420fcb5fec310f241a6b3d356..d9390472bf6fe0732d04a9cffdb66432fb42934e 100644 (file)
--- a/litesata/phy/datapath.py
+++ b/litesata/phy/datapath.py
@@ -36,9 +36,9 @@ class LiteSATAPHYDatapathRX(Module):
                ]
 
        # clock domain crossing
-               # (SATA3) 300MHz sata_rx clk to sys_clk
-               # (SATA2) 150MHz sata_rx clk to sys_clk
-               # (SATA1) 75MHz sata_rx clk to sys_clk
+               # (sata_gen3) 300MHz sata_rx clk to sys_clk
+               # (sata_gen2) 150MHz sata_rx clk to sys_clk
+               # (sata_gen1) 75MHz sata_rx clk to sys_clk
                # requirements:
                # due to the convertion ratio of 2, sys_clk need to be > sata_rx/2
                # source destination is always able to accept data (ack always 1)
@@ -58,9 +58,9 @@ class LiteSATAPHYDatapathTX(Module):
                ###
 
        # clock domain crossing
-               # (SATA3) sys_clk to 300MHz sata_tx clk
-               # (SATA2) sys_clk to 150MHz sata_tx clk
-               # (SATA1) sys_clk to 75MHz sata_tx clk
+               # (sata_gen3) sys_clk to 300MHz sata_tx clk
+               # (sata_gen2) sys_clk to 150MHz sata_tx clk
+               # (sata_gen1) sys_clk to 75MHz sata_tx clk
                # requirements:
                # source destination is always able to accept data (ack always 1)
                fifo = AsyncFIFO(phy_description(32), 4)

diff --git a/litesata/phy/k7/crg.py b/litesata/phy/k7/crg.py
index 9830b45b9147f5b88d23236bcab6e0b30ea38bc5..02592cf0137e0fa86cfb76df28b27f813026bdbe 100644 (file)
--- a/litesata/phy/k7/crg.py
+++ b/litesata/phy/k7/crg.py
@@ -9,8 +9,8 @@ class K7LiteSATAPHYCRG(Module):
                self.clock_domains.cd_sata_rx = ClockDomain()
 
        # CPLL
-               # (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps
-               # (SATA2 & SATA1) VCO still @ 3 GHz, Line rate is decreased with output dividers.
+               # (sata_gen3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps
+               # (sata_gen2 & sata_gen1) VCO still @ 3 GHz, Line rate is decreased with output dividers.
                refclk = Signal()
                self.specials += Instance("IBUFDS_GTE2",
                        i_CEB=0,
@@ -21,18 +21,18 @@ class K7LiteSATAPHYCRG(Module):
                self.comb += gtx.gtrefclk0.eq(refclk)
 
        # TX clocking
-               # (SATA3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits)
-               # (SATA2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits)
-               # (SATA1) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 75MHz (16-bits)
+               # (sata_gen3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits)
+               # (sata_gen2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits)
+               # (sata_gen1) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 75MHz (16-bits)
                mmcm_reset = Signal()
                mmcm_locked = Signal()
                mmcm_fb = Signal()
                mmcm_clk_i = Signal()
                mmcm_clk0_o = Signal()
                mmcm_div_config = {
-                       "SATA1" :       16.0,
-                       "SATA2" :       8.0,
-                       "SATA3" :       4.0
+                       "sata_gen1" :   16.0,
+                       "sata_gen2" :   8.0,
+                       "sata_gen3" :   4.0
                        }
                mmcm_div = mmcm_div_config[revision]
                self.specials += [
@@ -60,9 +60,9 @@ class K7LiteSATAPHYCRG(Module):
                ]
 
        # RX clocking
-               # (SATA3) sata_rx recovered clk @ 300MHz from GTX RXOUTCLK
-               # (SATA2) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
-               # (SATA1) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
+               # (sata_gen3) sata_rx recovered clk @ 300MHz from GTX RXOUTCLK
+               # (sata_gen2) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
+               # (sata_gen1) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
                self.specials += [
                        Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
                ]

diff --git a/litesata/phy/k7/trx.py b/litesata/phy/k7/trx.py
index 14a3b14e3b9717802e07608033d84729b37ed6fc..5e0713df18971f881fb66f5040f15da50d7421ff 100644 (file)
--- a/litesata/phy/k7/trx.py
+++ b/litesata/phy/k7/trx.py
@@ -101,17 +101,17 @@ class K7LiteSATAPHYTRX(Module):
 
        # Config at startup
                div_config = {
-                       "SATA1" :       4,
-                       "SATA2" :       2,
-                       "SATA3" :       1
+                       "sata_gen1" :   4,
+                       "sata_gen2" :   2,
+                       "sata_gen3" :   1
                        }
                rxout_div = div_config[revision]
                txout_div = div_config[revision]
 
                cdr_config = {
-                       "SATA1" :       0x0380008BFF40100008,
-                       "SATA2" :       0x0388008BFF40200008,
-                       "SATA3" :       0X0380008BFF10200010
+                       "sata_gen1" :   0x0380008BFF40100008,
+                       "sata_gen2" :   0x0388008BFF40200008,
+                       "sata_gen3" :   0X0380008BFF10200010
                }
                rxcdr_cfg = cdr_config[revision]
 

diff --git a/make.py b/make.py
index 533333d9ae7ea1cba50efd6372b35ba384130fb6..bcd1a17a3aa4b8979d719bec8046198474b13413 100644 (file)
--- a/make.py
+++ b/make.py
@@ -83,7 +83,6 @@ if __name__ == "__main__":
 
 
        revision = soc.sata_phy.revision
-       frequency = frequencies[soc.sata_phy.revision]
        has_bist = hasattr(soc.sata, "bist")
        user_ports = len(soc.sata.crossbar.users)
 
@@ -97,11 +96,13 @@ A small footprint and configurable SATA core
           based on Migen/MiSoC
 
 ====== Building options: ======
-SATA revision: {} / {} MHz
+{} / {} Gbps
+System Clk: {} MHz (min: {} MHz)
 User ports: {}
 BIST: {}
 ===============================""".format(
-       revision, frequency,
+       revision.replace("sata_", "SATA "), bitrates[revision],
+       soc.clk_freq/1000000, frequencies[revision],
        user_ports,
        has_bist
        )

diff --git a/setup.py b/setup.py
index ec8de13413455e31c7c9b737bd656c564441b001..422d4f4fdac9e85e381aec232da428e3577204f1 100644 (file)
--- a/setup.py
+++ b/setup.py
@@ -15,7 +15,7 @@ if sys.version_info < required_version:
 setup(
        name="litesata",
        version="unknown",
-       description="Generic open-source SATA1/2/3 controller",
+       description="small footprint and configurable SATA gen1/2/3 core",
        long_description=README,
        author="Florent Kermarrec",
        author_email="florent@enjoy-digital.fr",

diff --git a/targets/bist.py b/targets/bist.py
index a62fdf0068af11b4205225a5df4750596cce2efb..348498e911d0f15cf5d7a5603bf2b2c3697dc7cc 100644 (file)
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -139,7 +139,7 @@ class BISTSoC(GenSoC, AutoCSR):
                self.submodules.crg = _CRG(platform)
 
                # SATA PHY/Core/Frontend
-               self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq)
+               self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
                self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
                self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True)
 

diff --git a/targets/core.py b/targets/core.py
index 55085c330dc8b8e9d34f13dfba5603636a321ef9..d2e5865992a51c3ff6e5048c5436fdd50193c50e 100644 (file)
--- a/targets/core.py
+++ b/targets/core.py
@@ -4,23 +4,17 @@ from litesata.common import *
 from litesata.phy import LiteSATAPHY
 from litesata import LiteSATA
 
-class _CRG(Module):
-       def __init__(self, platform):
-               self.clock_domains.cd_sys = ClockDomain()
-
 class LiteSATACore(Module):
        default_platform = "verilog_backend"
-
-       def __init__(self, platform):
-               clk_freq = 166*1000000
-               self.crg = _CRG(platform)
+       def __init__(self, platform, clk_freq=166*1000000, nports=4):
+               self.clk_freq = clk_freq
 
                # SATA PHY/Core/Frontend
-               self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq)
+               self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
                self.submodules.sata = LiteSATA(self.sata_phy)
 
                # Get user ports from crossbar
-               self.user_ports = self.sata.crossbar.get_ports(4)
+               self.user_ports = self.sata.crossbar.get_ports(nports)
 
        def get_ios(self):
                ios = set()