ARM: Turn on the page table walker on ARM in SE mode.

diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index f0d23445f4b024b030dbba10f649ed1daf46a131..fc6f51d84fd21946e159f7e737295ccb40a61496 100644 (file)
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -37,26 +37,22 @@
 #
 # Authors: Ali Saidi
 
-from m5.defines import buildEnv
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+from MemObject import MemObject
 
-if buildEnv['FULL_SYSTEM']:
-    from MemObject import MemObject
-
-    class ArmTableWalker(MemObject):
-        type = 'ArmTableWalker'
-        cxx_class = 'ArmISA::TableWalker'
-        port = Port("Port for TableWalker to do walk the translation with")
-        sys = Param.System(Parent.any, "system object parameter")
-        min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
-        max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
+class ArmTableWalker(MemObject):
+    type = 'ArmTableWalker'
+    cxx_class = 'ArmISA::TableWalker'
+    port = Port("Port for TableWalker to do walk the translation with")
+    sys = Param.System(Parent.any, "system object parameter")
+    min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
+    max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
 
 
 class ArmTLB(SimObject):
     type = 'ArmTLB'
     cxx_class = 'ArmISA::TLB'
     size = Param.Int(64, "TLB size")
-    if buildEnv['FULL_SYSTEM']:
-       walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
+    walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 3dee08fbe8ad2ee3d5d2eaee67c4630c99e1ad3e..fe3d84f6d241b48b81c62d0419bea4daac74fd71 100644 (file)
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -59,6 +59,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('miscregs.cc')
     Source('predecoder.cc')
     Source('nativetrace.cc')
+    Source('table_walker.cc')
     Source('tlb.cc')
     Source('utility.cc')
     Source('remote_gdb.cc')
@@ -76,7 +77,6 @@ if env['TARGET_ISA'] == 'arm':
         Source('system.cc')
         Source('vtophys.cc')
         Source('linux/system.cc')
-        Source('table_walker.cc')
         
         SimObject('ArmSystem.py')
     else:

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a03e445cfa578fe3aa5cfb503ca5011b0b832758..f824925f2dad57993591805fafe40447ab5bffa3 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -47,6 +47,7 @@
 
 #include "arch/arm/faults.hh"
 #include "arch/arm/pagetable.hh"
+#include "arch/arm/table_walker.hh"
 #include "arch/arm/tlb.hh"
 #include "arch/arm/utility.hh"
 #include "base/inifile.hh"
@@ -58,29 +59,24 @@
 #include "debug/TLBVerbose.hh"
 #include "mem/page_table.hh"
 #include "params/ArmTLB.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 
 #if FULL_SYSTEM
 #include "arch/arm/system.hh"
-#include "arch/arm/table_walker.hh"
 #endif
 
 using namespace std;
 using namespace ArmISA;
 
 TLB::TLB(const Params *p)
-    : BaseTLB(p), size(p->size)
-#if FULL_SYSTEM
-      , tableWalker(p->walker)
-#endif
-    , rangeMRU(1), bootUncacheability(false), miscRegValid(false)
+    : BaseTLB(p), size(p->size) , tableWalker(p->walker),
+    rangeMRU(1), bootUncacheability(false), miscRegValid(false)
 {
     table = new TlbEntry[size];
     memset(table, 0, sizeof(TlbEntry) * size);
 
-#if FULL_SYSTEM
     tableWalker->setTlb(this);
-#endif
 }
 
 TLB::~TLB()
@@ -404,7 +400,6 @@ TLB::regStats()
     accesses = readAccesses + writeAccesses + instAccesses;
 }
 
-#if !FULL_SYSTEM
 Fault
 TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
         Translation *translation, bool &delay, bool timing)
@@ -426,18 +421,18 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
         }
     }
 
+#if !FULL_SYSTEM
     Addr paddr;
     Process *p = tc->getProcessPtr();
 
     if (!p->pTable->translate(vaddr, paddr))
         return Fault(new GenericPageTableFault(vaddr));
     req->setPaddr(paddr);
+#endif
 
     return NoFault;
 }
 
-#else // FULL_SYSTEM
-
 Fault
 TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
 {
@@ -578,10 +573,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
         }
     }
 
-
+#if FULL_SYSTEM
     if (!bootUncacheability &&
             ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
         req->setFlags(Request::UNCACHEABLE);
+#endif
 
     switch ( (dacr >> (te->domain * 2)) & 0x3) {
       case 0:
@@ -684,18 +680,15 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
     return NoFault;
 }
 
-#endif
-
 Fault
 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
     bool delay = false;
     Fault fault;
-#if FULL_SYSTEM
-    fault = translateFs(req, tc, mode, NULL, delay, false);
-#else
-    fault = translateSe(req, tc, mode, NULL, delay, false);
-#endif
+    if (FullSystem)
+        fault = translateFs(req, tc, mode, NULL, delay, false);
+    else
+        fault = translateSe(req, tc, mode, NULL, delay, false);
     assert(!delay);
     return fault;
 }
@@ -707,11 +700,10 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     assert(translation);
     bool delay = false;
     Fault fault;
-#if FULL_SYSTEM
-    fault = translateFs(req, tc, mode, translation, delay, true);
-#else
-    fault = translateSe(req, tc, mode, translation, delay, true);
-#endif
+    if (FullSystem)
+        fault = translateFs(req, tc, mode, translation, delay, true);
+    else
+        fault = translateSe(req, tc, mode, translation, delay, true);
     DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
             NoFault);
     if (!delay)
@@ -724,11 +716,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 Port*
 TLB::getPort()
 {
-#if FULL_SYSTEM
     return tableWalker->getPort("port");
-#else
-    return NULL;
-#endif
 }
 
 

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 3464e42b3a2412e5bcc745e696fb5827a5aee2ed..0bf13fe830bc31b320405f7b84e062ddb0df456d 100644 (file)
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -89,9 +89,7 @@ class TLB : public BaseTLB
 
     uint32_t _attr;     // Memory attributes for last accessed TLB entry
 
-#if FULL_SYSTEM
     TableWalker *tableWalker;
-#endif
 
     /** Lookup an entry in the TLB
      * @param vpn virtual address
@@ -195,13 +193,10 @@ class TLB : public BaseTLB
         return _attr;
     }
 
-#if FULL_SYSTEM
     Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
             Translation *translation, bool &delay, bool timing);
-#else
     Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
             Translation *translation, bool &delay, bool timing);
-#endif
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     Fault translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 43035600444ed493eefe287c0df25bfe32675204..277a2c8b4e004f58bb9ef7b52d23b6459782e30a 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -140,8 +140,7 @@ class BaseCPU(MemObject):
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
     _cached_ports = []
-    if buildEnv['TARGET_ISA'] == 'x86' or \
-        (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']):
+    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
         _cached_ports = ["itb.walker.port", "dtb.walker.port"]
 
     _uncached_ports = []
@@ -169,16 +168,15 @@ class BaseCPU(MemObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
-        if buildEnv['FULL_SYSTEM']:
-            if buildEnv['TARGET_ISA'] == 'x86':
-                self.itb_walker_cache = iwc
-                self.dtb_walker_cache = dwc
-                self.itb.walker.port = iwc.cpu_side
-                self.dtb.walker.port = dwc.cpu_side
-                self._cached_ports += ["itb_walker_cache.mem_side", \
-                                       "dtb_walker_cache.mem_side"]
-            elif buildEnv['TARGET_ISA'] == 'arm':
-                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+        if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc:
+            self.itb_walker_cache = iwc
+            self.dtb_walker_cache = dwc
+            self.itb.walker.port = iwc.cpu_side
+            self.dtb.walker.port = dwc.cpu_side
+            self._cached_ports += ["itb_walker_cache.mem_side", \
+                                   "dtb_walker_cache.mem_side"]
+        elif buildEnv['TARGET_ISA'] == 'arm':
+            self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)