"aghi\t%0,%h2"
[(set_attr "op_type" "RI")])
+(define_insn "*adddi3_carry1_cc"
+ [(set (reg 33)
+ (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DI 2 "general_operand" "d,m"))
+ (match_dup 1)))
+ (set (match_operand:DI 0 "register_operand" "=d,d")
+ (plus:DI (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
+ "@
+ algr\t%0,%2
+ alg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+(define_insn "*adddi3_carry1_cconly"
+ [(set (reg 33)
+ (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DI 2 "general_operand" "d,m"))
+ (match_dup 1)))
+ (clobber (match_scratch:DI 0 "=d,d"))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
+ "@
+ algr\t%0,%2
+ alg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+(define_insn "*adddi3_carry2_cc"
+ [(set (reg 33)
+ (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DI 2 "general_operand" "d,m"))
+ (match_dup 2)))
+ (set (match_operand:DI 0 "register_operand" "=d,d")
+ (plus:DI (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
+ "@
+ algr\t%0,%2
+ alg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+(define_insn "*adddi3_carry2_cconly"
+ [(set (reg 33)
+ (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DI 2 "general_operand" "d,m"))
+ (match_dup 2)))
+ (clobber (match_scratch:DI 0 "=d,d"))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
+ "@
+ algr\t%0,%2
+ alg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
(define_insn "*adddi3_cc"
[(set (reg 33)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
(clobber (match_scratch:SI 0 "=d,d,d"))]
- "s390_match_ccmode(insn, CCLmode)"
+ "s390_match_ccmode (insn, CCLmode)"
"@
alr\t%0,%2
al\t%0,%2
ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
-(define_insn "*addsi3_sub"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
- (clobber (reg:CC 33))]
- ""
- "@
- ah\t%0,%2
- ahy\t%0,%2"
- [(set_attr "op_type" "RX,RXY")])
-
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
slgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+(define_insn "*subdi3_borrow_cc"
+ [(set (reg 33)
+ (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:DI 2 "general_operand" "d,m"))
+ (match_dup 1)))
+ (set (match_operand:DI 0 "register_operand" "=d,d")
+ (minus:DI (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
+ "@
+ slgr\t%0,%2
+ slg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+(define_insn "*subdi3_borrow_cconly"
+ [(set (reg 33)
+ (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:DI 2 "general_operand" "d,m"))
+ (match_dup 1)))
+ (clobber (match_scratch:DI 0 "=d,d"))]
+ "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
+ "@
+ slgr\t%0,%2
+ slg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
(define_insn "*subdi3_cc"
[(set (reg 33)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCLmode)"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgr\t%0,%2
slg\t%0,%2"
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCLmode)"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgr\t%0,%2
slg\t%0,%2"
(match_dup 1)))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCL2mode)"
+ "s390_match_ccmode (insn, CCL2mode)"
"@
slr\t%0,%2
sl\t%0,%2
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
- "s390_match_ccmode(insn, CCL2mode)"
+ "s390_match_ccmode (insn, CCL2mode)"
"@
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXE")])
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cc"
[(set (reg 33)
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCLmode)"
+ "s390_match_ccmode (insn, CCLmode)"
"@
slr\t%0,%2
sl\t%0,%2
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
- "s390_match_ccmode(insn, CCLmode)"
+ "s390_match_ccmode (insn, CCLmode)"
"@
slr\t%0,%2
sl\t%0,%2
shy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
-(define_insn "*subsi3_sub"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
- (clobber (reg:CC 33))]
- ""
- "@
- sh\t%0,%2
- shy\t%0,%2"
- [(set_attr "op_type" "RX,RXY")])
-
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0")