soc: avoid double definition of main_ram

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index f20d6ecb748b85f52d774fda19a09d4b1a7551e5..42eab475caffe8f239ccc81d3f6663c9f788829a 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -958,7 +958,7 @@ class LiteXSoC(SoC):
         elif self.with_wishbone:
             # Wishbone Slave SDRAM interface -------------------------------------------------------
             wb_sdram = wishbone.Interface()
-            self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size))
+            self.bus.add_slave("main_ram", wb_sdram)
 
             # L2 Cache -----------------------------------------------------------------------------
             if l2_cache_size != 0: