pan/midgard: Fix 32/64 mixed swizzle packing

Occurs in SSBO address computation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c
index 1db5980e374eb341eb810ad8fa1db245e1813576..4d58217ceeb96fab140f28e4528009b31cb82f1c 100644 (file)
--- a/src/panfrost/midgard/midgard_emit.c
+++ b/src/panfrost/midgard/midgard_emit.c
@@ -194,8 +194,13 @@ mir_pack_swizzle_alu(midgard_instruction *ins)
                         packed = mir_pack_swizzle_64(ins->swizzle[i], components);
 
                         if (mode == midgard_reg_mode_32) {
-                                src[i].rep_low |= (ins->swizzle[i][0] >= COMPONENT_Z);
-                                src[i].rep_high |= (ins->swizzle[i][1] >= COMPONENT_Z);
+                                bool lo = ins->swizzle[i][0] >= COMPONENT_Z;
+                                bool hi = ins->swizzle[i][1] >= COMPONENT_Z;
+
+                                /* TODO: can we mix halves? */
+                                assert(lo == hi);
+
+                                src[i].rep_low |= lo;
                         } else if (mode < midgard_reg_mode_32) {
                                 unreachable("Cannot encode 8/16 swizzle in 64-bit");
                         }