(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 11ed17be9b6f02a589694d3f92adec79e49d73f8..f631b58e34758a4d7989d692c27b8296886acd05 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -17,7 +17,7 @@ Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, which was designed
 primarily for vectors of arithmetic and logical operations. However
 if predicates may be bits of CR Fields it makes sense to extend
-SVP64 to cover CR Operations.
+Simple-V to cover CR Operations.
 
 Element width however is clearly meaningless for a 4-bit
 collation of Conditions, EQ LT GE SO. Likewise, arithmetic saturation
@@ -34,7 +34,7 @@ Instructions that involve Rc=1 are definitively arithmetic in nature,
 where the corresponding Condition Register Field can be considered to
 be a "co-result". Such CR Field "co-result" arithmeric operations
 are firmly out of scope for
-this section.
+this section, being covered fully by [[sv/normal]].
 
 * Examples of v3.0B instructions to which this section does
   apply is
@@ -68,6 +68,12 @@ allows the decision to be made to store or not store the main
 result, and for CR Ops the CR Field result *is*
 the main result.
 
+*Programmer's note: 
+`sv.crxor` with reduction would be particularly useful for parity calculation
+for example, although there are many ways in which the same calculation
+could be carried out after transferring a vector of CR Fields to a GPR
+using crweird operations.*
+
 # Format
 
 SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations: