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AVX-512. Add vshufpd insn patterns.
authorAlexander Ivchenko <alexander.ivchenko@intel.com>
Tue, 23 Sep 2014 07:21:32 +0000 (07:21 +0000)
committerKirill Yukhin <kyukhin@gcc.gnu.org>
Tue, 23 Sep 2014 07:21:32 +0000 (07:21 +0000)
gcc/
* config/i386/sse.md
(define_expand "avx_shufpd256<mask_expand4_name>"): Add masking.
(define_insn "avx_shufpd256_1<mask_name>"): Ditto.
(define_expand "sse2_shufpd<mask_expand4_name>"): Ditto.
(define_insn "sse2_shufpd_v2df_mask"): New.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r215496

gcc/ChangeLog patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 090a9877e401696ca539c51ace9d6a296e4fc34c..ca76b1750443011b4a6101268d3a88cdbaee9857 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2014-09-23  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/i386/sse.md
+       (define_expand "avx_shufpd256<mask_expand4_name>"): Add masking.
+       (define_insn "avx_shufpd256_1<mask_name>"): Ditto.
+       (define_expand "sse2_shufpd<mask_expand4_name>"): Ditto.
+       (define_insn "sse2_shufpd_v2df_mask"): New.
+
 2014-09-23  Alexander Ivchenko  <alexander.ivchenko@intel.com>
            Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
            Anna Tikhonova  <anna.tikhonova@intel.com>
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9151063c4ba4579a7c55d08113a58fb9d445b751..9e0c0e82b433aa0da0fc376b6d1e5f02c9079a31 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7790,7 +7790,7 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "V8DF")])
 
-(define_expand "avx_shufpd256"
+(define_expand "avx_shufpd256<mask_expand4_name>"
   [(match_operand:V4DF 0 "register_operand")
    (match_operand:V4DF 1 "register_operand")
    (match_operand:V4DF 2 "nonimmediate_operand")
@@ -7798,25 +7798,28 @@
   "TARGET_AVX"
 {
   int mask = INTVAL (operands[3]);
-  emit_insn (gen_avx_shufpd256_1 (operands[0], operands[1], operands[2],
-                                  GEN_INT (mask & 1),
-                                  GEN_INT (mask & 2 ? 5 : 4),
-                                  GEN_INT (mask & 4 ? 3 : 2),
-                                  GEN_INT (mask & 8 ? 7 : 6)));
+  emit_insn (gen_avx_shufpd256_1<mask_expand4_name> (operands[0],
+                                                    operands[1],
+                                                    operands[2],
+                                                    GEN_INT (mask & 1),
+                                                    GEN_INT (mask & 2 ? 5 : 4),
+                                                    GEN_INT (mask & 4 ? 3 : 2),
+                                                    GEN_INT (mask & 8 ? 7 : 6)
+                                                    <mask_expand4_args>));
   DONE;
 })
 
-(define_insn "avx_shufpd256_1"
-  [(set (match_operand:V4DF 0 "register_operand" "=x")
+(define_insn "avx_shufpd256_1<mask_name>"
+  [(set (match_operand:V4DF 0 "register_operand" "=v")
        (vec_select:V4DF
          (vec_concat:V8DF
-           (match_operand:V4DF 1 "register_operand" "x")
-           (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
+           (match_operand:V4DF 1 "register_operand" "v")
+           (match_operand:V4DF 2 "nonimmediate_operand" "vm"))
          (parallel [(match_operand 3 "const_0_to_1_operand")
                     (match_operand 4 "const_4_to_5_operand")
                     (match_operand 5 "const_2_to_3_operand")
                     (match_operand 6 "const_6_to_7_operand")])))]
-  "TARGET_AVX"
+  "TARGET_AVX && <mask_avx512vl_condition>"
 {
   int mask;
   mask = INTVAL (operands[3]);
@@ -7825,14 +7828,14 @@
   mask |= (INTVAL (operands[6]) - 6) << 3;
   operands[3] = GEN_INT (mask);
 
-  return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+  return "vshufpd\t{%3, %2, %1, %0<mask_operand7>|%0<mask_operand7>, %1, %2, %3}";
 }
   [(set_attr "type" "sseshuf")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4DF")])
 
-(define_expand "sse2_shufpd"
+(define_expand "sse2_shufpd<mask_expand4_name>"
   [(match_operand:V2DF 0 "register_operand")
    (match_operand:V2DF 1 "register_operand")
    (match_operand:V2DF 2 "nonimmediate_operand")
@@ -7840,12 +7843,38 @@
   "TARGET_SSE2"
 {
   int mask = INTVAL (operands[3]);
-  emit_insn (gen_sse2_shufpd_v2df (operands[0], operands[1], operands[2],
-                               GEN_INT (mask & 1),
-                               GEN_INT (mask & 2 ? 3 : 2)));
+  emit_insn (gen_sse2_shufpd_v2df<mask_expand4_name> (operands[0], operands[1],
+                                                     operands[2], GEN_INT (mask & 1),
+                                                     GEN_INT (mask & 2 ? 3 : 2)
+                                                     <mask_expand4_args>));
   DONE;
 })
 
+(define_insn "sse2_shufpd_v2df_mask"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
+    (vec_merge:V2DF
+         (vec_select:V2DF
+           (vec_concat:V4DF
+             (match_operand:V2DF 1 "register_operand" "v")
+             (match_operand:V2DF 2 "nonimmediate_operand" "vm"))
+           (parallel [(match_operand 3 "const_0_to_1_operand")
+                          (match_operand 4 "const_2_to_3_operand")]))
+      (match_operand:V2DF 5 "vector_move_operand" "0C")
+      (match_operand:QI 6 "register_operand" "Yk")))]
+  "TARGET_AVX512VL"
+{
+  int mask;
+  mask = INTVAL (operands[3]);
+  mask |= (INTVAL (operands[4]) - 2) << 1;
+  operands[3] = GEN_INT (mask);
+
+  return "vshufpd\t{%3, %2, %1, %0%{%6%}%N5|%0%{6%}%N5, %1, %2, %3}";
+}
+  [(set_attr "type" "sseshuf")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "V2DF")])
+
 ;; punpcklqdq and punpckhqdq are shorter than shufpd.
 (define_insn "avx2_interleave_highv4di<mask_name>"
   [(set (match_operand:V4DI 0 "register_operand" "=v")