Rename $currQ to $abc9_currQ

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 4f6491311d43e7d55479eff0d1567b66c7d23fd8..03246a9b509cad72f421e100e85b0b8530002cd7 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -479,11 +479,11 @@ struct XAigerWriter
                                        }
                                }
 
-                               // Connect <cell>.$currQ (inserted by abc9_map.v) as an input to the flop box
+                               // Connect <cell>.$abc9_currQ (inserted by abc9_map.v) as an input to the flop box
                                if (box_module->get_bool_attribute("\\abc9_flop")) {
-                                       SigSpec rhs = module->wire(stringf("%s.$currQ", cell->name.c_str()));
+                                       SigSpec rhs = module->wire(stringf("%s.$abc9_currQ", cell->name.c_str()));
                                        if (rhs.empty())
-                                               log_error("'%s.$currQ' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
+                                               log_error("'%s.$abc9_currQ' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
 
                                        int offset = 0;
                                        for (auto b : rhs) {
@@ -496,7 +496,7 @@ struct XAigerWriter
                                                        else
                                                                alias_map[b] = I;
                                                }
-                                               co_bits.emplace_back(b, cell, "\\$currQ", offset++, 0);
+                                               co_bits.emplace_back(b, cell, "\\$abc9_currQ", offset++, 0);
                                                unused_bits.erase(b);
                                        }
                                }
@@ -787,7 +787,7 @@ struct XAigerWriter
                                }
 
                                // For flops only, create an extra 1-bit input that drives a new wire
-                               //   called "<cell>.$currQ" that is used below
+                               //   called "<cell>.$abc9_currQ" that is used below
                                if (box_module->get_bool_attribute("\\abc9_flop")) {
                                        log_assert(holes_cell);
 
@@ -799,7 +799,7 @@ struct XAigerWriter
                                                holes_wire->port_id = port_id++;
                                                holes_module->ports.push_back(holes_wire->name);
                                        }
-                                       Wire *w = holes_module->addWire(stringf("%s.$currQ", cell->name.c_str()));
+                                       Wire *w = holes_module->addWire(stringf("%s.$abc9_currQ", cell->name.c_str()));
                                        holes_module->connect(w, holes_wire);
                                }
 
@@ -884,9 +884,9 @@ struct XAigerWriter
                                                log_assert(pos != std::string::npos);
                                                IdString driver = Q.wire->name.substr(0, pos);
                                                // And drive the signal that was previously driven by "DFF.Q" (typically
-                                               //   used to implement clock-enable functionality) with the "<cell>.$currQ"
+                                               //   used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
                                                //   wire (which itself is driven an input port) we inserted above
-                                               Wire *currQ = holes_module->wire(stringf("%s.$currQ", driver.c_str()));
+                                               Wire *currQ = holes_module->wire(stringf("%s.$abc9_currQ", driver.c_str()));
                                                log_assert(currQ);
                                                holes_module->connect(Q, currQ);
                                                continue;

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index feaf979ada074f45f250e7d2173d9cbc97c23d12..ee319a8e3fcd176cf8444ced54bcd01a80c56d8d 100644 (file)
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -35,34 +35,34 @@
 //   order to extract the combinatorial control logic left behind.
 //   Specifically, a simulation model similar to the one below:
 //
-//           ++===================================++
-//           ||                        Sim model  ||
-//           ||      /\/\/\/\                     ||
-//       D -->>-----<        >     +------+       ||
-//       R -->>-----<  Comb. >     |$_DFF_|       ||
-//      CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
-//           ||  +--<        >     +------+   |   ||
-//           ||  |   \/\/\/\/                 |   ||
-//           ||  |                            |   ||
-//           ||  +----------------------------+   ||
-//           ||                                   ||
-//           ++===================================++
+//                ++===================================++
+//                ||                        Sim model  ||
+//                ||      /\/\/\/\                     ||
+//            D -->>-----<        >     +------+       ||
+//            R -->>-----<  Comb. >     |$_DFF_|       ||
+//           CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
+//                ||  +--<        >     +------+   |   ||
+//                ||  |   \/\/\/\/                 |   ||
+//                ||  |                            |   ||
+//                ||  +----------------------------+   ||
+//                ||                                   ||
+//                ++===================================++
 //
 //   is transformed into:
 //
-//           ++==================++
-//           ||         Comb box ||
-//           ||                  ||
-//           ||      /\/\/\/\    ||
-//      D  -->>-----<        >   ||            +------+
-//      R  -->>-----<  Comb. >   ||            |$_ABC_|
-//     CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
-// $currQ +-->>-----<        >   ||            +------+  |
-//        |  ||      \/\/\/\/    ||                      |
-//        |  ||                  ||                      |
-//        |  ++==================++                      |
-//        |                                              |
-//        +----------------------------------------------+
+//                ++==================++
+//                ||         Comb box ||
+//                ||                  ||
+//                ||      /\/\/\/\    ||
+//           D  -->>-----<        >   ||            +------+
+//           R  -->>-----<  Comb. >   ||            |$_ABC_|
+//          CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
+// $abc9_currQ +-->>-----<        >   ||            +------+  |
+//             |  ||      \/\/\/\/    ||                      |
+//             |  ||                  ||                      |
+//             |  ++==================++                      |
+//             |                                              |
+//             +----------------------------------------------+
 //
 // The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
@@ -74,7 +74,7 @@
 // (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control 
 //     domain (which, combined with this cell type, encodes to `abc9' which
 //     flops may be merged together)
-// (d) a special _TECHMAP_REPLACE_.$currQ wire that will be used for feedback
+// (d) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -95,7 +95,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -110,7 +110,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
@@ -118,7 +118,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire $nextQ, $currQ;
+  wire $nextQ, $abc9_currQ;
   FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -131,19 +131,19 @@ module FDCE (output reg Q, input C, CE, D, CLR);
                                          //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC9_ASYNC box by abc9_map.v
-  \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  wire _TECHMAP_REPLACE_.$currQ = $currQ;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  wire $nextQ, $currQ;
+  wire $nextQ, $abc9_currQ;
   FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
@@ -153,13 +153,13 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
                                          //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  wire _TECHMAP_REPLACE_.$currQ = $currQ;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
@@ -167,7 +167,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire $nextQ, $currQ;
+  wire $nextQ, $abc9_currQ;
   FDPE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -180,17 +180,17 @@ module FDPE (output reg Q, input C, CE, D, PRE);
                                          //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  wire _TECHMAP_REPLACE_.$currQ = $currQ;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
-  wire $nextQ, $currQ;
+  wire $nextQ, $abc9_currQ;
   FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
@@ -200,13 +200,13 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
                                          //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  wire _TECHMAP_REPLACE_.$currQ = $currQ;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
@@ -228,7 +228,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
@@ -243,7 +243,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
 module RAM32X1D (