.*: b2 18 5f ff [ ]*pc 4095\(%r5\)
.*: b2 2e 00 69 [ ]*pgin %r6,%r9
.*: b2 2f 00 69 [ ]*pgout %r6,%r9
-.*: e9 ff 5f ff af ff [ ]*pka 4095\(256,%r5\),4095\(%r10\)
+.*: e9 1f 5f ff af ff [ ]*pka 4095\(%r5\),4095\(32,%r10\)
.*: e1 ff 5f ff af ff [ ]*pku 4095\(256,%r5\),4095\(%r10\)
.*: ee 69 5f ff af ff [ ]*plo %r6,4095\(%r5\),%r9,4095\(%r10\)
.*: 01 01 [ ]*pr
#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */
#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
+#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */
#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
b278 stcke S_RD "store clock extended" g5 esa,zarch
b2a5 tre RRE_RR "translate extended" g5 esa,zarch
eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch
-e9 pka SS_L0RDRD "pack ascii" g5 esa,zarch
+e9 pka SS_L2RDRD "pack ascii" g5 esa,zarch
e1 pku SS_L0RDRD "pack unicode" g5 esa,zarch
b993 troo RRE_RR "translate one to one" g5 esa,zarch
b992 trot RRE_RR "translate one to two" g5 esa,zarch