gdb/arm: fix IPSR field test in arm_m_exception_cache ()

Arm v8-M Architecture Reference Manual,
D1.2.141 IPSR, Interrupt Program Status Register reads
"Exception, bits [8:0]"

9 bits, not 8! It is uncommon but true!

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index ae0882f9c4a1f5ed9dd71b0c3686ed0b5e2c4de1..247e5522b8e417aa534ef4311189944c88602249 100644 (file)
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -3441,7 +3441,7 @@ arm_m_exception_cache (frame_info_ptr this_frame)
        }
 
       ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
-      if ((xpsr & 0xff) != 0)
+      if ((xpsr & 0x1ff) != 0)
        /* Handler mode: This is the mode that exceptions are handled in.  */
        arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum);
       else