remove not needed top module

diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v
index 0605bd102ddd727902c9714bfe768abd4ab83f5b..368fbaace5e8a1e87b98b937646cc700f049c241 100644 (file)
--- a/tests/xilinx/fsm.v
+++ b/tests/xilinx/fsm.v
@@ -52,22 +52,4 @@
  endcase\r
  end\r
 \r
- endmodule\r
-\r
- module top (\r
-input clk,\r
-input rst,\r
-input a,\r
-input b,\r
-output g0,\r
-output g1\r
-);\r
-\r
-fsm u_fsm ( .clock(clk),\r
-            .reset(rst),\r
-            .req_0(a),\r
-            .req_1(b),\r
-            .gnt_0(g0),\r
-            .gnt_1(g1));\r
-\r
 endmodule\r

diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys
index 3b73891c2149358182a034bed67ed6291d4407b9..a9e94c2c0f91fc5aaea46334f5f958a8278d43a8 100644 (file)
--- a/tests/xilinx/fsm.ys
+++ b/tests/xilinx/fsm.ys
@@ -1,10 +1,10 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
 flatten
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:BUFG
 select -assert-count 5 t:FDRE