Increase UART bridge speed in simulation, decrease simulation time

diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index e0089356a32274d33bcca87648f53a07d0539f2f..486b8313df199ca8fb1867bfcc7976364bd98c2b 100644 (file)
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -26,7 +26,7 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
-        self.ub = UARTBridge(divisor=217, pins=platform.request("uart", 0))
+        self.ub = UARTBridge(divisor=5, pins=platform.request("uart", 0))
         self._arbiter.add(self.ub.bus)
 
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"})))

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 74395a158181d9ae17b886873c414fd1f7fa0a86..ac8bdbd08ee6ff813bf3b259a76b45e47292cee0 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -114,7 +114,7 @@ module simsoctb;
     begin
       uart_rx <= 1'b1;
       $display("[%t] Starting POR",$time);
-      #100; // POR is ~700us
+      #1000; // POR is ~700us
       $display("[%t] POR complete",$time);
 
       // Software control
@@ -216,14 +216,14 @@ module simsoctb;
 
     begin
       uart_rx <= 1'b0;
-      #2170;
+      #50;
       for (i = 0; i < 8; i = i + 1)
         begin
           uart_rx <= data[i];
-          #2170;
+          #50;
         end
       uart_rx <= 1'b1;
-      #2170;
+      #50;
     end
   endtask
 
@@ -239,10 +239,10 @@ module simsoctb;
 
       for (i = 0; i < 8; i = i+1)
         begin
-          #2170 data[i] <= uart_tx;
+          #50 data[i] <= uart_tx;
         end
 
-      #2170;
+      #50;
     end
   endtask
 endmodule