sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)

diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py
index ed199a028b2909fdd94add752cc69219adad7872..e61973ca7350c53ef231b00a2c752edabaca8610 100644 (file)
--- a/misoclib/mem/sdram/core/lasmicon/__init__.py
+++ b/misoclib/mem/sdram/core/lasmicon/__init__.py
@@ -9,14 +9,13 @@ from misoclib.mem.sdram.core.lasmicon.multiplexer import *
 class LASMIconSettings:
        def __init__(self, req_queue_size=8,
                        read_time=32, write_time=16,
-                       with_l2=True, l2_size=8192,
+                       l2_size=8192,
                        with_bandwidth=False,
                        with_memtest=False,
                        with_refresh=True):
                self.req_queue_size = req_queue_size
                self.read_time = read_time
                self.write_time = write_time
-               self.with_l2 = with_l2
                self.l2_size = l2_size
                if with_memtest:
                        self.with_bandwidth = True

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 72f82f78e5b8c2be956afdf24f1a0cbb44e7d97a..e8227c954ceb2c6419973ce91e334d089976e7ca 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -53,8 +53,8 @@ class SDRAMSoC(SoC):
                                self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
                                self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
 
-                       if self.sdram_controller_settings.with_l2:
-                               l2_size = self.sdram_controller_settings.l2_size
+                       l2_size = self.sdram_controller_settings.l2_size
+                       if l2_size != 0:
                                # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
                                # Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
                                # Remove this workaround when fixed by Xilinx.