X86: Implement STMXCSR.

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 7d955eb3eb6351ab6f5230f7be2b1f55237a428a..5d817d2c20cb81e2bb6d5d4e5cae783d701d2c05 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -829,7 +829,7 @@
                     0x0: fxsave();
                     0x1: fxrstor();
                     0x2: ldmxcsr();
-                    0x3: stmxcsr();
+                    0x3: Inst::STMXCSR(Md);
                     0x4: Inst::UD2();
                     0x5: decode MODRM_MOD {
                         0x3: BasicOperate::LFENCE(

diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
index 687391b47d675f6de7480d6639e1865ad4e3b1c3..831a266c79003999922cc9d0fecf96d38a82a4a5 100644 (file)
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
@@ -54,6 +54,15 @@
 # Authors: Gabe Black
 
 microcode = '''
-# STMXCSR
+def macroop STMXCSR_M {
+    rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+    st t1, seg, sib, disp
+};
+
+def macroop STMXCSR_P {
+    rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+    rdip t7
+    st t1, seg, riprel, disp
+};
 # LDMXCSR
 '''