(no commit message)

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index c50e3f4959f72e5c10c41e4b9f735a59904f7617..ec093afaafa79fa5dbdff0abe7687aa5babfca02 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -24,44 +24,56 @@ If you violate any of the above stated hard-and-fast rules you will end up learn
 
 To start we have to ensure we have a safe set up.
 
-* Ensure power is disconnected from FPGA
-* Ensure STLINKV2 USB is disconnected
-* Ensure FPGA USB is disconnected
+| Done?   | Checklist Step |
+|---------|----------------|
+|         | Ensure power is disconnected from FPGA |
+|         | Ensure STLINKV2 USB is disconnected |
+|         | Ensure FPGA USB is disconnected |
+
+Now lets review all of the relevant material on this page before we begin the wiring process.
 
 | Done?   | Checklist Step |
 |---------|----------------|
 |         | Review the STLINKv2 Connector diagram and table |
 |         | Review the connections table for your model of fpga |
 |         | Make sure the orientation of your FPGA board and your STLINKv2 are the same as the images and diagrams on this page |
-|         | Wire each of the coloured jumper cables to the corresponding pins on the FPGA and the STLINKv2 according to the diagrams, tables, and images on this page. Below are separate checklist for each model of FPGA |
 
-ADD TABLE CONNECTING STLINK MALE-TO-FEMALE JUMPERS HERE.  START WITH DUPLICATE COPY OF ULX3S TABLE AND REMOVE "(ULX3S PIN #N)"
+Next we will wire up the STLINKv2 and our FPGA in three separate stages. First attaching a FEMALE-TO-FEMALE jumper cable to each male header pin on the STLINKv2. Then attaching a ***COMPLETELY DIFFERENT*** FEMALE-TO-FEMALE jumper cable to each male header pin on the FPGA. Finally, we will use MALE-TO-MALE jumper cables to connect the wires from the STLINKv2 to the wires from the FPGA. This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of each of the two devices so that the wires do not randomly damage the STLINKv2 due to a short.
 
-Follow this section if you have the ULX3S FPGA:
+We will wire each of the pins on the the STLINKv2 according to the diagrams, tables, and images on this page. 
 
 | Done?   | Checklist Step |
 |---------|----------------|
-|         | Wire the **RED** jumper cable to (**ULX3S pin #2**) then wire it to (**STLINKv2 pin #2**), this will serve as the **Voltage Reference** signal (**VREF**) 
+|         | Attach one end of a FEMALE-TO-FEMALE **RED** jumper cable to (**STLINKv2 pin #2**), this will serve as the **Voltage Reference** signal (**VREF**) 
+|         | Attach one end of a FEMALE-TO-FEMALE **BLACK** jumper cable to (**STLINKv2 pin #4**), this will serve as the **Ground** signal (**GND**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **GREEN** jumper cable to (**STLINKv2 pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **BLUE** jumper cable to (**STLINKv2 pin #7**), this will serve as the **Test Mode Select** signal (**TMS**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **WHITE** jumper cable to  (**STLINKv2 pin #9**), this will serve as the **Test Clock** signal (**TCK**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **YELLOW** jumper cable to (**STLINKv2 pin #13**), this will serve as the **Test Data Out** signal (**TDO**)
 
-REMOVE MENTION OF STLINK FROM HERE.  REQUIRE JUMPER TO BE FEMALETOFEMALE.
-  REPEAT FOR ALL TABLE ENTRIES
+Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
 
-|         | Wire the **BLACK** jumper cable to (**ULX3S pin #4**) then wire it to (**STLINKv2 pin #4**), this will serve as the **Ground** signal (**GND**) |
-|         | Wire the **GREEN** jumper cable to (**ULX3S pin #5**) then wire it to (**STLINKv2 pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
-|         | Wire the **BLUE** jumper cable to (**ULX3S pin #6**) then wire it to (**STLINKv2 pin #7**), this will serve as the **Test Mode Select** signal (**TMS**) |
-|         | Wire the **WHITE** jumper cable to (**ULX3S pin #7**) then wire it to (**STLINKv2 pin #9**), this will serve as the **Test Clock** signal (**TCK**) |
-|         | Wire the **YELLOW** jumper cable to (**ULX3S pin #8**) then wire it to (**STLINKv2 pin #13**), this will serve as the **Test Data Out** signal (**TDO**) |
+Follow this section if you have the ULX3S FPGA:
+
+| Done?   | Checklist Step |
+|---------|----------------|
+|         | Attach one end of a FEMALE-TO-FEMALE **RED** jumper cable to (**ULX3S pin #2**), this will serve as the **Voltage Reference** signal (**VREF**) 
+|         | Attach one end of a FEMALE-TO-FEMALE **BLACK** jumper cable to (**ULX3S pin #4**), this will serve as the **Ground** signal (**GND**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **GREEN** jumper cable to (**ULX3S pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **BLUE** jumper cable to (**ULX3S pin #6**), this will serve as the **Test Mode Select** signal (**TMS**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **WHITE** jumper cable to (**ULX3S pin #7**), this will serve as the **Test Clock** signal (**TCK**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **YELLOW** jumper cable to (**ULX3S pin #8**), this will serve as the **Test Data Out** signal (**TDO**) |
 
 Follow this section if you have the Versa ECP5 FPGA:
 
 | Done?   | Checklist Step |
 |---------|----------------|
-|         | Wire the **RED** jumper cable to (**X3 pin #39**) then wire it to (**STLINKv2 pin #2**), this will serve as the **Voltage Reference** signal (**VREF**) |
-|         | Wire the **BLACK** jumper cable to (**X3 pin #1**) then wire it to (**STLINKv2 pin #4**), this will serve as the **Ground** signal (**GND**) |
-|         | Wire the **GREEN** jumper cable to (**X3 pin #4**) then wire it to (**STLINKv2 pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
-|         | Wire the **BLUE** jumper cable to (**X3 pin #5**) then wire it to (**STLINKv2 pin #7**), this will serve as the **Test Mode Select** signal (**TMS**) |
-|         | Wire the **WHITE** jumper cable to (**X3 pin #6**) then wire it to (**STLINKv2 pin #9**), this will serve as the **Test Clock** signal (**TCK**) |
-|         | Wire the **YELLOW** jumper cable to (**X3 pin #7**) then wire it to (**STLINKv2 pin #13**), this will serve as the **Test Data Out** signal (**TDO**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **RED** jumper cable to (**X3 pin #39**), this will serve as the **Voltage Reference** signal (**VREF**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **BLACK** jumper cable to (**X3 pin #1**), this will serve as the **Ground** signal (**GND**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **GREEN** jumper cable to (**X3 pin #4**), this will serve as the **Test Data In** signal (**TDI**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **BLUE** jumper cable to (**X3 pin #5**), this will serve as the **Test Mode Select** signal (**TMS**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **WHITE** jumper cable to (**X3 pin #6**), this will serve as the **Test Clock** signal (**TCK**) |
+|         | Attach one end of a FEMALE-TO-FEMALE **YELLOW** jumper cable to (**X3 pin #7**), this will serve as the **Test Data Out** signal (**TDO**) |
 
 Final steps for both FPGA boards:
 
@@ -71,6 +83,18 @@ Final steps for both FPGA boards:
 |         | ***lckl*** check for ground loops? |
 
 
+Finally, we will connect the unattached ends of each of the FEMALE-TO-FEMALE jumper cables on the STLINKv2 and FPGA together using MALE-TO-MALE jumper cables.
+
+| Done?   | Checklist Step |
+|---------|----------------|
+|         | Attach one end of a MALE-TO-MALE **RED** jumper cable to the **RED** FEMALE-TO-FEMALE jumper cable coming from the STLINKv2. Connect the other end of the MALE-TO-MALE **RED** jumper cable to the **RED** FEMALE-TO-FEMALE jumper cable coming from the FPGA |
+|         | Attach one end of a MALE-TO-MALE **BLACK** jumper cable to the **BLACK** FEMALE-TO-FEMALE jumper cable coming from the STLINKv2. Connect the other end of the MALE-TO-MALE **BLACK** jumper cable to the **BLACK** FEMALE-TO-FEMALE jumper cable coming from the FPGA |
+|         | Attach one end of a MALE-TO-MALE **GREEN** jumper cable to the **GREEN** FEMALE-TO-FEMALE jumper cable coming from the STLINKv2. Connect the other end of the MALE-TO-MALE **GREEN** jumper cable to the **GREEN** FEMALE-TO-FEMALE jumper cable coming from the FPGA |
+|         | Attach one end of a MALE-TO-MALE **BLUE** jumper cable to the **BLUE** FEMALE-TO-FEMALE jumper cable coming from the STLINKv2. Connect the other end of the MALE-TO-MALE **BLUE** jumper cable to the **BLUE** FEMALE-TO-FEMALE jumper cable coming from the FPGA |
+|         | Attach one end of a MALE-TO-MALE **WHITE** jumper cable to the **WHITE** FEMALE-TO-FEMALE jumper cable coming from the STLINKv2. Connect the other end of the MALE-TO-MALE **WHITE** jumper cable to the **WHITE** FEMALE-TO-FEMALE jumper cable coming from the FPGA |
+|         | Attach one end of a MALE-TO-MALE **YELLOW** jumper cable to the **YELLOW** FEMALE-TO-FEMALE jumper cable coming from the STLINKv2. Connect the other end of the MALE-TO-MALE **YELLOW** jumper cable to the **YELLOW** FEMALE-TO-FEMALE jumper cable coming from the FPGA |
+
+
 ## Connecting the dots:
 
 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>