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diff --git a/nlnet_2021_crypto_router.mdwn b/nlnet_2021_crypto_router.mdwn
index 0f18c361fcce0a71cfaff1780f4a3da4fdb82b01..455d74c15f2118d430457c80aa1b7cbba8c95e12 100644 (file)
--- a/nlnet_2021_crypto_router.mdwn
+++ b/nlnet_2021_crypto_router.mdwn
@@ -35,6 +35,7 @@ Ultimately we want a demonstration ASIC of an independently-auditable hardware i
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
 NLnet is backing the Libre-SOC project with a number of PET Grants (ending this year).  So far we have, thanks to NLnet:
+
 * Implemented the integer OpenPOWER ISA in a libre-compatible Lattice FPGA (ECP5)
 * Provided Formal Correctness proofs for all OpenPOWER pipelines implemented so far
 * Implemented a parameteriseable IEEE754 HDL library including SQRT, RSQRT and CORDIC pipelines and run several hundred thousand unit tests.
@@ -57,7 +58,7 @@ EUR $50,000.
     operations and Galois Field arithmetic, as well as ternary bitmanipulation
     and Carry-capable Vector "long arithmetic".
 * Hardware implementation of the underlying instruction primitives and Vector-Matrix concepts needed to support the crypto-primitives used in blockchain algorithms
-* Proof of Concept software implementation of the hashing algorithms identified, showing how Vectorised Matrix manipulation atvthe ISA level can greatly simplify the readability and clarity of cryptography, for aydit purposes.
+* Proof of Concept software implementation of the hashing algorithms identified, showing how Vectorised Matrix manipulation at the ISA level can greatly simplify the readability and clarity of cryptography, for audit purposes.
 * Formal Correctness proofs of the underlying hardware instruction primitives
 * Implementation of RGMII and USB-ULPI in nmigen
 * Implementation in nmigen of a DMA Engine suitable for Ethernet Frame packet transfer