soc_core: add JTAG UART support (uart_name="jtag_uart)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index e46e7c61525de98baac5b3c3fc6df48d2dbc3018..a8832da0c9e2819c6e9ddc5ed9f145bdf6e80983 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -318,6 +318,9 @@ class SoCCore(Module):
                 if uart_name == "jtag_atlantic":
                     from litex.soc.cores.jtag import JTAGAtlantic
                     self.submodules.uart_phy = JTAGAtlantic()
+                elif uart_name == "jtag_uart":
+                    from litex.soc.cores.jtag import JTAGPHY
+                    self.submodules.uart_phy = JTAGPHY(device=platform.device)
                 else:
                     self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
                 self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))