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radeonsi: fix VGT_PRIMITIVE_TYPE emit for CIK
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 28 Sep 2012 21:35:26 +0000 (17:35 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 28 Jun 2013 19:15:54 +0000 (15:15 -0400)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
src/gallium/drivers/radeonsi/si_state_draw.c patch | blob | history

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 09c741fa3f13b8bb5cafe5813a61ebe5b94bc3c1..234f66155fb57d0ba3f387c5333f4e233064febe 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -285,7 +285,10 @@ static bool si_update_draw_info_state(struct r600_context *rctx,
                return false;
        }
 
-       si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
+       if (rctx->chip_class >= CIK)
+               si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
+       else
+               si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
        si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
        si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
        si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,