(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 4a15058a9b2147121354a1baa6acdd27c4d057c7..13b27ff73e5748a848d4edeae2b47fc9570ac920 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -909,7 +909,7 @@ Instructions are broken down by Register Profiles as listed in the
 following auto-generated page: [[opcode_regs_deduped]].  These tables,
 despite being auto-generated, are part of the Specification.
 
-# SV pseudocode illilustration
+# SV pseudocode illustration
 
 ## Single-predicated Instruction
 
@@ -927,8 +927,7 @@ overrides not included.  if there is no predicate, it is set to all 1s
         if (rd.isvec)  { id += 1; }
         if (rs1.isvec) { irs1 += 1; }
         if (rs2.isvec) { irs2 += 1; }
-        if (id == VL or irs1 == VL or irs2 == VL)
-        {
+        if (id == VL or irs1 == VL or irs2 == VL) {
           # end VL hardware loop
           STATE.srcoffs = 0; # reset
           return;