use new core domain variable in TestRunnerBase

and add the dbgsync domain back in

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index cc91b75ddeda2604335343e9054e38b882474844..1bce1f39ac6fe66df47d1fb948ea6a1148471dda 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -151,6 +151,7 @@ class TestRunnerBase(FHDLTestCase):
                              xics=False,
                              gpio=False,
                              regreduce=not self.allow_overlap,
+                             core_domain="sync", # no alternative domain
                              svp64=self.svp64,
                              allow_overlap=self.allow_overlap,
                              mmu=self.microwatt_mmu,
@@ -181,6 +182,8 @@ class TestRunnerBase(FHDLTestCase):
         # but Simulation-only fails without it
         intclk = ClockSignal("coresync")
         comb += intclk.eq(ClockSignal())
+        dbgclk = ClockSignal("dbgsync")
+        comb += dbgclk.eq(ClockSignal())
 
         # nmigen Simulation - everything runs around this, so it
         # still has to be created.