---------- Begin Simulation Statistics ----------
-sim_seconds 1.898954 # Number of seconds simulated
-sim_ticks 1898954186500 # Number of ticks simulated
-final_tick 1898954186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.896908 # Number of seconds simulated
+sim_ticks 1896907607500 # Number of ticks simulated
+final_tick 1896907607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 93254 # Simulator instruction rate (inst/s)
-host_op_rate 93254 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3072830921 # Simulator tick rate (ticks/s)
+host_inst_rate 91997 # Simulator instruction rate (inst/s)
+host_op_rate 91997 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3111116066 # Simulator tick rate (ticks/s)
host_mem_usage 330780 # Number of bytes of host memory used
-host_seconds 617.98 # Real time elapsed on the host
-sim_insts 57629320 # Number of instructions simulated
-sim_ops 57629320 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 946048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24721152 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 36608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 493888 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28848320 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 946048 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 36608 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 982656 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7831936 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7831936 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 14782 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 386268 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 572 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 7717 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 450755 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 122374 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122374 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 498194 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13018298 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1395834 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 19278 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 260084 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15191688 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 498194 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 19278 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 517472 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4124342 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4124342 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4124342 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 498194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13018298 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1395834 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 19278 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 260084 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19316030 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 450755 # Total number of read requests seen
-system.physmem.writeReqs 122374 # Total number of write requests seen
-system.physmem.cpureqs 604625 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28848320 # Total number of bytes read from memory
-system.physmem.bytesWritten 7831936 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28848320 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7831936 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 7306 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28435 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28036 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28258 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28415 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 28091 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 28033 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 28162 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28315 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27858 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::13 28166 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 28158 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 28038 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7848 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7611 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7694 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7488 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7537 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7442 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7588 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7788 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7389 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7747 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7895 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7671 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::14 7650 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7483 # Track writes on a per bank basis
+host_seconds 609.72 # Real time elapsed on the host
+sim_insts 56092592 # Number of instructions simulated
+sim_ops 56092592 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 788928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24066944 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2649408 # Number of bytes read from this memory
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+system.physmem.bytes_read::cpu1.data 1095360 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28794304 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 788928 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 193664 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 982592 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7762048 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7762048 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 12327 # Number of read requests responded to by this memory
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+system.physmem.num_writes::writebacks 121282 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 121282 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 415902 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12687462 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1396698 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 102095 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::total 15179603 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 415902 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 517997 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4091948 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4091948 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::total 19271551 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 449911 # Total number of read requests seen
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+system.physmem.bytesRead 28794304 # Total number of bytes read from memory
+system.physmem.bytesWritten 7762048 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28794304 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7762048 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 53 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 3357 # Reqs where no action is needed
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1898947634000 # Total gap between requests
+system.physmem.numWrRetry 313 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1896888917000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 450755 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 8153093 # DTB read hits
-system.cpu0.dtb.read_misses 30801 # DTB read misses
-system.cpu0.dtb.read_acv 546 # DTB read access violations
-system.cpu0.dtb.read_accesses 631302 # DTB read accesses
-system.cpu0.dtb.write_hits 5186191 # DTB write hits
-system.cpu0.dtb.write_misses 6023 # DTB write misses
-system.cpu0.dtb.write_acv 347 # DTB write access violations
-system.cpu0.dtb.write_accesses 217125 # DTB write accesses
-system.cpu0.dtb.data_hits 13339284 # DTB hits
-system.cpu0.dtb.data_misses 36824 # DTB misses
-system.cpu0.dtb.data_acv 893 # DTB access violations
-system.cpu0.dtb.data_accesses 848427 # DTB accesses
-system.cpu0.itb.fetch_hits 954719 # ITB hits
-system.cpu0.itb.fetch_misses 30502 # ITB misses
-system.cpu0.itb.fetch_acv 1031 # ITB acv
-system.cpu0.itb.fetch_accesses 985221 # ITB accesses
+system.cpu0.dtb.read_hits 7007258 # DTB read hits
+system.cpu0.dtb.read_misses 29214 # DTB read misses
+system.cpu0.dtb.read_acv 555 # DTB read access violations
+system.cpu0.dtb.read_accesses 627494 # DTB read accesses
+system.cpu0.dtb.write_hits 4619142 # DTB write hits
+system.cpu0.dtb.write_misses 6985 # DTB write misses
+system.cpu0.dtb.write_acv 345 # DTB write access violations
+system.cpu0.dtb.write_accesses 208744 # DTB write accesses
+system.cpu0.dtb.data_hits 11626400 # DTB hits
+system.cpu0.dtb.data_misses 36199 # DTB misses
+system.cpu0.dtb.data_acv 900 # DTB access violations
+system.cpu0.dtb.data_accesses 836238 # DTB accesses
+system.cpu0.itb.fetch_hits 888386 # ITB hits
+system.cpu0.itb.fetch_misses 27286 # ITB misses
+system.cpu0.itb.fetch_acv 998 # ITB acv
+system.cpu0.itb.fetch_accesses 915672 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 96359628 # number of cpu cycles simulated
+system.cpu0.numCycles 83155415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 11511160 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 9658650 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 337362 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 8089137 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 5013359 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 9804849 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 8272695 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 286303 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 6905955 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 4307856 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 738841 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 28813 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 22209501 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 59836413 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 11511160 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 5752200 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 11350991 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1703319 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 34574956 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 35024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 203611 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 316697 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7365602 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 218420 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 69794661 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.857321 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.189603 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 619842 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 27789 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 19011041 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 50915714 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 9804849 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4927698 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 9659436 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1473505 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 28455218 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 29555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 194299 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 211367 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 6349535 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 190370 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 58504859 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.870282 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.201063 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 58443670 83.74% 83.74% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 721745 1.03% 84.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1525948 2.19% 86.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 670208 0.96% 87.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2529232 3.62% 91.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 511055 0.73% 92.27% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 558087 0.80% 93.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 646305 0.93% 94.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4188411 6.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 48845423 83.49% 83.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 638375 1.09% 84.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1232766 2.11% 86.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 545499 0.93% 87.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2228588 3.81% 91.43% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 432839 0.74% 92.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 448017 0.77% 92.94% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 658155 1.12% 94.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3475197 5.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 69794661 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.119460 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.620970 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 23572170 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 33977525 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 10309860 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 863665 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1071440 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 494315 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 32656 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 58557743 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 90732 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1071440 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 24508121 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 14373596 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 16410684 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9644673 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3786145 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 55387876 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6888 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 592503 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1353497 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 37339158 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 67830341 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 67526671 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 303670 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 32375017 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4964141 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1283235 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 190076 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 10267361 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 8584787 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5466291 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1084962 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 724878 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 49128818 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1589448 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 47805943 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 98656 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5900406 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 3193389 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1078704 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 69794661 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.684951 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.331704 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 58504859 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.117910 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.612296 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 20221803 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 27858596 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 8736076 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 771700 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 916683 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 397847 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 27467 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 49800366 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 84499 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 916683 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 21025049 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 10730618 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 14396247 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 8233599 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3202661 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 46975607 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 6729 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 282251 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1314603 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 31610949 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 57450568 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 57189305 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 261263 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 27436892 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4174049 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1166690 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 177857 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 8656888 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7389019 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 4877617 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 925746 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 640404 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 41641305 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1430691 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 40525941 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 100515 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 4996937 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 2778091 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 970759 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 58504859 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.692694 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.328093 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 48560473 69.58% 69.58% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 9626391 13.79% 83.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4360326 6.25% 89.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2905573 4.16% 93.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2277062 3.26% 97.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1128487 1.62% 98.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 610541 0.87% 99.53% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 278212 0.40% 99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 47596 0.07% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 40198625 68.71% 68.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 8496961 14.52% 83.23% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3824833 6.54% 89.77% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2421122 4.14% 93.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1801555 3.08% 96.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 974491 1.67% 98.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 509636 0.87% 99.53% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 241631 0.41% 99.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 36005 0.06% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 69794661 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 58504859 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 83272 13.43% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 13.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 288642 46.54% 59.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 248279 40.03% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 54985 10.35% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 255079 48.00% 58.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 221355 41.65% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 33277792 69.61% 69.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 52563 0.11% 69.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 13047 0.03% 69.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 8484999 17.75% 87.51% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5253957 10.99% 98.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 718601 1.50% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 27833265 68.68% 68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 41848 0.10% 68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 13219 0.03% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 7301690 18.02% 86.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 4678009 11.54% 98.39% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 652246 1.61% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 47805943 # Type of FU issued
-system.cpu0.iq.rate 0.496120 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 620193 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.012973 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 165689680 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 56419476 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 46799675 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 435716 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 211307 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 205983 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 48194794 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 228014 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 514272 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 40525941 # Type of FU issued
+system.cpu0.iq.rate 0.487352 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 531419 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013113 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 139814106 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 47896052 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 39650626 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 374568 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 182665 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 177037 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 40857986 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 195589 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 455505 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1137404 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2618 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 12330 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 467046 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1004949 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2086 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 10010 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 405892 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 18608 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 143062 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 11959 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 139790 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1071440 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 10277613 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 727728 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 53688552 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 610167 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 8584787 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5466291 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1400307 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 521112 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 4713 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 12330 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 181936 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 316829 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 498765 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 47397397 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 8205181 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 408546 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 916683 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 7413565 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 614240 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 45518060 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 556785 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7389019 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 4877617 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1263664 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 539342 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 5760 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 10010 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 149941 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 281478 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 431419 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 40181745 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 7054742 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 344195 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 2970286 # number of nop insts executed
-system.cpu0.iew.exec_refs 13410008 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 7582856 # Number of branches executed
-system.cpu0.iew.exec_stores 5204827 # Number of stores executed
-system.cpu0.iew.exec_rate 0.491880 # Inst execution rate
-system.cpu0.iew.wb_sent 47094366 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 47005658 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 23624719 # num instructions producing a value
-system.cpu0.iew.wb_consumers 31676204 # num instructions consuming a value
+system.cpu0.iew.exec_nop 2446064 # number of nop insts executed
+system.cpu0.iew.exec_refs 11690884 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 6330042 # Number of branches executed
+system.cpu0.iew.exec_stores 4636142 # Number of stores executed
+system.cpu0.iew.exec_rate 0.483213 # Inst execution rate
+system.cpu0.iew.wb_sent 39909560 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 39827663 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 19855593 # num instructions producing a value
+system.cpu0.iew.wb_consumers 26361633 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.487815 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.745819 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.478955 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.753200 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6363159 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 510744 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 465851 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 68723221 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.687218 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.593416 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 5375485 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 459932 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 404147 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 57588176 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.695477 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.605159 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 50805017 73.93% 73.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7482510 10.89% 84.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 4158339 6.05% 90.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2211388 3.22% 94.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1226271 1.78% 95.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 519535 0.76% 96.62% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 434174 0.63% 97.26% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 401210 0.58% 97.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1484777 2.16% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 42371011 73.58% 73.58% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 6488229 11.27% 84.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 3374360 5.86% 90.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1907115 3.31% 94.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1044719 1.81% 95.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 416558 0.72% 96.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 355194 0.62% 97.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 347785 0.60% 97.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1283205 2.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 68723221 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 47227841 # Number of instructions committed
-system.cpu0.commit.committedOps 47227841 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 57588176 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 40051259 # Number of instructions committed
+system.cpu0.commit.committedOps 40051259 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 12446628 # Number of memory references committed
-system.cpu0.commit.loads 7447383 # Number of loads committed
-system.cpu0.commit.membars 170869 # Number of memory barriers committed
-system.cpu0.commit.branches 7170885 # Number of branches committed
-system.cpu0.commit.fp_insts 203520 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 43794871 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 589410 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1484777 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 10855795 # Number of memory references committed
+system.cpu0.commit.loads 6384070 # Number of loads committed
+system.cpu0.commit.membars 151085 # Number of memory barriers committed
+system.cpu0.commit.branches 6007416 # Number of branches committed
+system.cpu0.commit.fp_insts 174841 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 37190024 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 489523 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1283205 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 120629648 # The number of ROB reads
-system.cpu0.rob.rob_writes 108253472 # The number of ROB writes
-system.cpu0.timesIdled 983557 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26564967 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3700831730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 44545141 # Number of Instructions Simulated
-system.cpu0.committedOps 44545141 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 44545141 # Number of Instructions Simulated
-system.cpu0.cpi 2.163191 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.163191 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.462280 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.462280 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 62595782 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34216642 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 100415 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 101247 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1454133 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 720721 # number of misc regfile writes
+system.cpu0.rob.rob_reads 101537476 # The number of ROB reads
+system.cpu0.rob.rob_writes 91770556 # The number of ROB writes
+system.cpu0.timesIdled 793139 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 24650556 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3710654942 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 37835874 # Number of Instructions Simulated
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+system.cpu0.cpi_total 2.197793 # CPI: Total CPI of All Threads
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system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
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system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit.
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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 22364.222790 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43843.196966 # average WriteReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 33593.137562 # average overall miss latency
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-system.cpu0.dcache.blocked::no_mshrs 46334 # number of cycles access was blocked
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+system.cpu0.dcache.occ_percent::total 0.934242 # Average percentage of cache occupancy
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system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.writebacks::total 669951 # number of writebacks
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12333.246183 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12333.246183 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4181.250000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4181.250000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2751784 # DTB read hits
-system.cpu1.dtb.read_misses 11470 # DTB read misses
-system.cpu1.dtb.read_acv 7 # DTB read access violations
-system.cpu1.dtb.read_accesses 320817 # DTB read accesses
-system.cpu1.dtb.write_hits 1920140 # DTB write hits
-system.cpu1.dtb.write_misses 2953 # DTB write misses
-system.cpu1.dtb.write_acv 42 # DTB write access violations
-system.cpu1.dtb.write_accesses 122077 # DTB write accesses
-system.cpu1.dtb.data_hits 4671924 # DTB hits
-system.cpu1.dtb.data_misses 14423 # DTB misses
-system.cpu1.dtb.data_acv 49 # DTB access violations
-system.cpu1.dtb.data_accesses 442894 # DTB accesses
-system.cpu1.itb.fetch_hits 498760 # ITB hits
-system.cpu1.itb.fetch_misses 8025 # ITB misses
-system.cpu1.itb.fetch_acv 112 # ITB acv
-system.cpu1.itb.fetch_accesses 506785 # ITB accesses
+system.cpu1.dtb.read_hits 3713266 # DTB read hits
+system.cpu1.dtb.read_misses 14359 # DTB read misses
+system.cpu1.dtb.read_acv 33 # DTB read access violations
+system.cpu1.dtb.read_accesses 328215 # DTB read accesses
+system.cpu1.dtb.write_hits 2351870 # DTB write hits
+system.cpu1.dtb.write_misses 2326 # DTB write misses
+system.cpu1.dtb.write_acv 62 # DTB write access violations
+system.cpu1.dtb.write_accesses 130566 # DTB write accesses
+system.cpu1.dtb.data_hits 6065136 # DTB hits
+system.cpu1.dtb.data_misses 16685 # DTB misses
+system.cpu1.dtb.data_acv 95 # DTB access violations
+system.cpu1.dtb.data_accesses 458781 # DTB accesses
+system.cpu1.itb.fetch_hits 552396 # ITB hits
+system.cpu1.itb.fetch_misses 7861 # ITB misses
+system.cpu1.itb.fetch_acv 226 # ITB acv
+system.cpu1.itb.fetch_accesses 560257 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 23450533 # number of cpu cycles simulated
+system.cpu1.numCycles 34615367 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 3776767 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 3137470 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 107427 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 2636449 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 1329693 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 5312293 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 4360790 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 184753 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 3627578 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 1933378 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 256698 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 10696 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 9578000 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 17862357 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 3776767 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1586391 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 3193569 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 532728 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 8846684 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 29714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 64849 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 64234 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.CacheLines 2092153 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 72512 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 22109536 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.807903 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.182028 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 383381 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 19114 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 12153279 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 25592027 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 5312293 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 2316759 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 4666723 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 848042 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 13957627 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 25440 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 65073 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 147747 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 2992364 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 115997 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 31571084 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.810616 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.170872 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 18915967 85.56% 85.56% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 225371 1.02% 86.58% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 332195 1.50% 88.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 235368 1.06% 89.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 429129 1.94% 91.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 160604 0.73% 91.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 176264 0.80% 92.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 387732 1.75% 94.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 1246906 5.64% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 26904361 85.22% 85.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 276998 0.88% 86.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 593564 1.88% 87.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 353090 1.12% 89.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 710175 2.25% 91.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 234476 0.74% 92.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 277213 0.88% 92.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 377383 1.20% 94.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 1843824 5.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 22109536 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.161053 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.761704 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 9287856 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 9344742 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 2981707 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 172176 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 323054 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 161936 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 9554 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 17577560 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 27080 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 323054 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 9598975 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 567037 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 7834145 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 2842462 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 943861 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 16294411 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 85147 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 230847 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 10570715 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 19279832 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 19004281 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 275551 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 9242282 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1328425 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 653029 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 73319 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 2960053 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 2891333 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 2010374 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 258927 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 184993 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 14228135 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 747471 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 13980669 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 34327 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1780795 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 830376 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 520995 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 22109536 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.632337 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.304677 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 31571084 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.153466 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.739326 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 12173556 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 14265063 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 4322746 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 271541 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 538177 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 245868 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 17179 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 25069869 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 51217 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 538177 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 12622413 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 4307697 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 8552551 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 4022106 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 1528138 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 23469307 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 403073 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 318746 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 15460907 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 27951432 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 27722595 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 228837 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 13017644 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 2443263 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 711049 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 79879 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 4546986 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 3946391 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 2480141 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 398992 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 247125 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 20556503 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 873226 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 19920635 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 45889 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 3011838 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 1481780 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 622079 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 31571084 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.630977 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.308978 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 15925897 72.03% 72.03% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 2876428 13.01% 85.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 1188641 5.38% 90.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 788361 3.57% 93.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 710967 3.22% 97.20% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 312206 1.41% 98.61% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 203719 0.92% 99.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 91872 0.42% 99.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 11445 0.05% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 22947759 72.69% 72.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 3816292 12.09% 84.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 1671768 5.30% 90.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 1218822 3.86% 93.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 1072376 3.40% 97.33% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 425454 1.35% 98.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 262904 0.83% 99.51% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 135529 0.43% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 20180 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 22109536 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 31571084 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 4072 1.54% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 138321 52.40% 53.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 121563 46.05% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 28274 8.56% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 166109 50.30% 58.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 135868 41.14% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3973 0.03% 0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 8718475 62.36% 62.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 23525 0.17% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 14518 0.10% 62.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1986 0.01% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 2887601 20.65% 83.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1950660 13.95% 97.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 379931 2.72% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 13189448 66.21% 66.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 28632 0.14% 66.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 12556 0.06% 66.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 3884810 19.50% 85.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 2385812 11.98% 97.92% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 414088 2.08% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 13980669 # Type of FU issued
-system.cpu1.iq.rate 0.596177 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 263956 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.018880 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 49973211 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 16565755 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 13576031 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 395945 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 192396 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 186883 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 14033908 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 206744 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 127652 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 19920635 # Type of FU issued
+system.cpu1.iq.rate 0.575485 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 330251 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.016578 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 71458593 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 24286363 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 19388343 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 329901 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 159417 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 155652 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 20074577 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 172783 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 184439 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 343707 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 718 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 1847 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 149646 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 581301 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 1183 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 4340 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 230089 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 8933 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 6918 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 18073 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 323054 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 323914 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 83587 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 15804070 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 217247 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 2891333 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 2010374 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 666348 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 75335 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2938 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 1847 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 54178 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 138289 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 192467 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 13856768 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 2775542 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 123900 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 538177 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 3253999 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 229517 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 22699099 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 268114 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 3946391 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 2480141 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 779721 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 89744 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2529 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 4340 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 96593 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 181110 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 277703 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 19708494 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 3738657 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 212141 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 828464 # number of nop insts executed
-system.cpu1.iew.exec_refs 4708126 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 2079937 # Number of branches executed
-system.cpu1.iew.exec_stores 1932584 # Number of stores executed
-system.cpu1.iew.exec_rate 0.590894 # Inst execution rate
-system.cpu1.iew.wb_sent 13794604 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 13762914 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 6356145 # num instructions producing a value
-system.cpu1.iew.wb_consumers 9022133 # num instructions consuming a value
+system.cpu1.iew.exec_nop 1269370 # number of nop insts executed
+system.cpu1.iew.exec_refs 6100523 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 3128191 # Number of branches executed
+system.cpu1.iew.exec_stores 2361866 # Number of stores executed
+system.cpu1.iew.exec_rate 0.569357 # Inst execution rate
+system.cpu1.iew.wb_sent 19587937 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 19543995 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 9462232 # num instructions producing a value
+system.cpu1.iew.wb_consumers 13383566 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.586891 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.704506 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.564605 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.707004 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1892811 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 226476 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 180279 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 21786482 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.634671 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.584399 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 3264810 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 251147 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 260251 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 31032907 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.624350 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.557822 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 16693912 76.63% 76.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 2323450 10.66% 87.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 881751 4.05% 91.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 546550 2.51% 93.85% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 424121 1.95% 95.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 149663 0.69% 96.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 143043 0.66% 97.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 194342 0.89% 98.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 429650 1.97% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 23883562 76.96% 76.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 2995086 9.65% 86.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1581522 5.10% 91.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 799862 2.58% 94.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 502768 1.62% 95.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 236983 0.76% 96.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 224339 0.72% 97.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 194617 0.63% 98.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 614168 1.98% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 21786482 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 13827253 # Number of instructions committed
-system.cpu1.commit.committedOps 13827253 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 31032907 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 19375400 # Number of instructions committed
+system.cpu1.commit.committedOps 19375400 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 4408354 # Number of memory references committed
-system.cpu1.commit.loads 2547626 # Number of loads committed
-system.cpu1.commit.membars 77059 # Number of memory barriers committed
-system.cpu1.commit.branches 1974738 # Number of branches committed
-system.cpu1.commit.fp_insts 185573 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 12741220 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 216858 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 429650 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 5615142 # Number of memory references committed
+system.cpu1.commit.loads 3365090 # Number of loads committed
+system.cpu1.commit.membars 85627 # Number of memory barriers committed
+system.cpu1.commit.branches 2912516 # Number of branches committed
+system.cpu1.commit.fp_insts 154287 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 17850043 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 300496 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 614168 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 36982885 # The number of ROB reads
-system.cpu1.rob.rob_writes 31761465 # The number of ROB writes
-system.cpu1.timesIdled 211192 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 1340997 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3774455201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 13084179 # Number of Instructions Simulated
-system.cpu1.committedOps 13084179 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 13084179 # Number of Instructions Simulated
-system.cpu1.cpi 1.792282 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.792282 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.557948 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.557948 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 17801475 # number of integer regfile reads
-system.cpu1.int_regfile_writes 9673582 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 97896 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 98917 # number of floating regfile writes
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-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30003.227783 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 30003.227783 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9948.222715 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9948.222715 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.269365 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.269365 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22367.215652 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 22367.215652 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22367.215652 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 22367.215652 # average overall miss latency
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+system.cpu1.dcache.sampled_refs 521257 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 8.610831 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 31290571500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 498.284346 # Average occupied blocks per requestor
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+system.cpu1.dcache.occ_percent::total 0.973212 # Average percentage of cache occupancy
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15331.324875 # average ReadReq miss latency
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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 4032 # number of cycles access was blocked
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system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 122264 # number of writebacks
-system.cpu1.dcache.writebacks::total 122264 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 218997 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 218997 # number of ReadReq MSHR hits
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-system.cpu1.dcache.WriteReq_mshr_hits::total 293003 # number of WriteReq MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 512000 # number of overall MSHR hits
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-system.cpu1.dcache.overall_mshr_misses::total 193058 # number of overall MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049398 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049398 # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.142490 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11855.792476 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11855.792476 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24475.714395 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24475.714395 # average WriteReq mshr miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.814185 # average LoadLockedReq mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16201.493815 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16201.493815 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16201.493815 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 405697 # number of writebacks
+system.cpu1.dcache.writebacks::total 405697 # number of writebacks
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+system.cpu1.dcache.ReadReq_mshr_hits::total 310580 # number of ReadReq MSHR hits
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.143641 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.143641 # mshr miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.091960 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.091960 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13142.481754 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13142.481754 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28285.126824 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28285.126824 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12153.549383 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12153.549383 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5261.973875 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5261.973875 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6891 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 160705 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 55206 40.22% 40.22% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 141 0.10% 40.32% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1925 1.40% 41.72% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 459 0.33% 42.06% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 79532 57.94% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 137263 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 54744 49.07% 49.07% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 141 0.13% 49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1925 1.73% 50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 459 0.41% 51.34% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 54290 48.66% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 111559 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1864428350500 98.20% 98.20% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 66694000 0.00% 98.20% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 571257500 0.03% 98.23% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 222612500 0.01% 98.25% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 33310195000 1.75% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1898599109500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.991631 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 4859 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 144961 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 48033 39.13% 39.13% # number of times we switched to this ipl
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+system.cpu0.kern.ipl_count::22 1924 1.57% 40.81% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 16 0.01% 40.82% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 72639 59.18% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 122745 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 47372 48.94% 48.94% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 133 0.14% 49.07% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1924 1.99% 51.06% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 16 0.02% 51.08% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 47357 48.92% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 96802 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1866486525500 98.40% 98.40% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 63938000 0.00% 98.40% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 572947000 0.03% 98.43% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 8827500 0.00% 98.43% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 29774513500 1.57% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1896906751500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.986239 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.682618 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.812739 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
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-system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
-system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
-system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
-system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
-system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
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-system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
-system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
-system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
-system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
-system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
-system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 222 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.651950 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.788643 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed
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+system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed
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+system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed
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+system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed
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+system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed
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+system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed
+system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed
+system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed
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+system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 211 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 540 0.37% 0.37% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.37% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.37% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 2997 2.06% 2.43% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.04% 2.47% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.47% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 130488 89.67% 92.14% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6655 4.57% 96.71% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed
-system.cpu0.kern.callpal::rti 4254 2.92% 99.64% # number of callpals executed
-system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 145528 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6813 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
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+system.cpu0.kern.callpal::total 130177 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 5807 # number of protection mode switches
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system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1282
-system.cpu0.kern.mode_good::user 1282
+system.cpu0.kern.mode_good::kernel 1286
+system.cpu0.kern.mode_good::user 1287
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.188170 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.221457 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.316739 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1896637292000 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1952797500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.362701 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1894993254500 99.90% 99.90% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 2998 # number of times the context was actually changed
+system.cpu0.kern.swap_context 2436 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2640 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 82284 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 28208 38.75% 38.75% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1924 2.64% 41.39% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 540 0.74% 42.13% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 42124 57.87% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 72796 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 27293 48.30% 48.30% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1924 3.40% 51.70% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 540 0.96% 52.66% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 26753 47.34% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 56510 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1872083396500 98.59% 98.59% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 532362500 0.03% 98.61% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 246280000 0.01% 98.63% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 26091314000 1.37% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1898953353000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.967562 # fraction of swpipl calls that actually changed the ipl
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+system.cpu1.kern.ipl_count::0 33560 40.13% 40.13% # number of times we switched to this ipl
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+system.cpu1.kern.ipl_count::30 97 0.12% 42.54% # number of times we switched to this ipl
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+system.cpu1.kern.ipl_good::0 32844 48.58% 48.58% # number of times we switched to this ipl from a different ipl
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+system.cpu1.kern.ipl_good::30 97 0.14% 51.56% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 32747 48.44% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 67609 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1867334401000 98.46% 98.46% # number of cycles we spent at this ipl
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+system.cpu1.kern.ipl_ticks::30 45472500 0.00% 98.49% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 28701925000 1.51% 100.00% # number of cycles we spent at this ipl
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system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.635101 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.776279 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
-system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
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-system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
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-system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
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-system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
-system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
-system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 104 # number of syscalls executed
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+system.cpu1.kern.ipl_used::total 0.808372 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed
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+system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed
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+system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed
+system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed
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+system.cpu1.kern.syscall::total 115 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 459 0.61% 0.61% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 2146 2.85% 3.47% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.00% 3.47% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 3.48% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 66489 88.37% 91.85% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2102 2.79% 94.64% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 94.64% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 94.65% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 94.65% # number of callpals executed
-system.cpu1.kern.callpal::rti 3842 5.11% 99.76% # number of callpals executed
-system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed
-system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1813 2.11% 2.13% # number of callpals executed
+system.cpu1.kern.callpal::tbi 6 0.01% 2.14% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 78432 91.18% 93.32% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2336 2.72% 96.04% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 96.04% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 3 0.00% 96.04% # number of callpals executed
+system.cpu1.kern.callpal::rdusp 1 0.00% 96.04% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.00% 96.05% # number of callpals executed
+system.cpu1.kern.callpal::rti 3185 3.70% 99.75% # number of callpals executed
+system.cpu1.kern.callpal::callsys 172 0.20% 99.95% # number of callpals executed
+system.cpu1.kern.callpal::imb 43 0.05% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 75240 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 2162 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2922 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 928
-system.cpu1.kern.mode_good::user 464
-system.cpu1.kern.mode_good::idle 464
-system.cpu1.kern.mode_switch_good::kernel 0.429232 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 86022 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 2264 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 459 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 518
+system.cpu1.kern.mode_good::user 459
+system.cpu1.kern.mode_good::idle 59
+system.cpu1.kern.mode_switch_good::kernel 0.228799 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.158795 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.334535 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 8174267000 0.43% 0.43% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 802919500 0.04% 0.47% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1889976158500 99.53% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 2147 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.028964 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.217647 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 42822911000 2.26% 2.26% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 817792500 0.04% 2.30% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1852963538500 97.70% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1814 # number of times the context was actually changed
---------- End Simulation Statistics ----------
sim_ticks 1854370484500 # Number of ticks simulated
final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94446 # Simulator instruction rate (inst/s)
-host_op_rate 94446 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3304859837 # Simulator tick rate (ticks/s)
-host_mem_usage 326668 # Number of bytes of host memory used
-host_seconds 561.10 # Real time elapsed on the host
+host_inst_rate 120780 # Simulator instruction rate (inst/s)
+host_op_rate 120780 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4226353954 # Simulator tick rate (ticks/s)
+host_mem_usage 326684 # Number of bytes of host memory used
+host_seconds 438.76 # Real time elapsed on the host
sim_insts 52993965 # Number of instructions simulated
sim_ops 52993965 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory
system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 6175508423 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13385774423 # Sum of mem lat for all requests
+system.physmem.totQLat 6175504423 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13385770423 # Sum of mem lat for all requests
system.physmem.totBusLat 1780884000 # Total cycles spent in databus access
system.physmem.totBankLat 5429382000 # Total cycles spent in bank access
-system.physmem.avgQLat 13870.66 # Average queueing delay per request
+system.physmem.avgQLat 13870.65 # Average queueing delay per request
system.physmem.avgBankLat 12194.80 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30065.46 # Average memory access latency
+system.physmem.avgMemAccLat 30065.45 # Average memory access latency
system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37395096 # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles 37395098 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 81356871 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 81356873 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67855364 83.40% 83.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 67855366 83.40% 83.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 81356871 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 81356873 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37116939 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 37116941 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing
system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19830183 # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles 19830185 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename
system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 81356871 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 81356873 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56509821 69.46% 69.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56509823 69.46% 69.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 81356871 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 81356873 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available
system.cpu.iq.rate 0.522738 # Inst issue rate
system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 195876832 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 195876834 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads
system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 80002696 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 80002698 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 59120918 73.90% 73.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 59120920 73.90% 73.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 80002696 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 80002698 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56184240 # Number of instructions committed
system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 740415 # Number of function calls committed.
system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 142220967 # The number of ROB reads
+system.cpu.rob.rob_reads 142220969 # The number of ROB reads
system.cpu.rob.rob_writes 129940455 # The number of ROB writes
system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 27974649 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 27974647 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 52993965 # Number of Instructions Simulated
system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated
system.cpu.dcache.overall_misses::total 3743164 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445086639 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 70445086639 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445061639 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 70445061639 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 104297759139 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 104297759139 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 104297759139 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 104297759139 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 104297734139 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 104297734139 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 104297734139 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 104297734139 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.547949 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.547949 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.535074 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.535074 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 27863.529126 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27863.529126 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 2571682 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 27863.522448 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27863.522448 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2571680 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946948 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946927 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712390769 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712390769 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712386769 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712386769 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907863269 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 31907863269 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907863269 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 31907863269 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907859269 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 31907859269 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907859269 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 31907859269 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997718998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997718998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421626998 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421626998 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997720998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997720998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421628998 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421628998 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.159135 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.159135 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.145811 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.145811 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 53963.120653 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 53963.120652 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496192000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 8496192000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496188000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 8496188000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 20300283500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 21216500500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 20300279500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 21216496500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 20300283500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 21216500500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 20300279500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 21216496500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.450111 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.450111 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.415427 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.415427 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52473.228551 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52473.218658 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52473.228551 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52473.218658 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067951103 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067951103 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067947103 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067947103 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327873464 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16052895904 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327869464 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16052891904 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327873464 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16052895904 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331389500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331389500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1881061000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1881061000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212450500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212450500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327869464 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16052891904 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333831000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333831000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882540500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882540500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216371500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216371500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.178458 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.178458 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.143774 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.143774 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.523636 # Number of seconds simulated
-sim_ticks 2523635852000 # Number of ticks simulated
-final_tick 2523635852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.523629 # Number of seconds simulated
+sim_ticks 2523629285500 # Number of ticks simulated
+final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 60184 # Simulator instruction rate (inst/s)
-host_op_rate 77414 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2506430956 # Simulator tick rate (ticks/s)
-host_mem_usage 399764 # Number of bytes of host memory used
-host_seconds 1006.86 # Real time elapsed on the host
-sim_insts 60597347 # Number of instructions simulated
-sim_ops 77945524 # Number of ops (including micro ops) simulated
+host_inst_rate 68763 # Simulator instruction rate (inst/s)
+host_op_rate 88448 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2863680529 # Simulator tick rate (ticks/s)
+host_mem_usage 399792 # Number of bytes of host memory used
+host_seconds 881.25 # Real time elapsed on the host
+sim_insts 60597236 # Number of instructions simulated
+sim_ops 77945371 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 799360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129436368 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 799360 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 799360 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory
+system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 56 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12490 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096909 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47367240 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1420 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 316749 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3604203 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51289637 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 316749 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316749 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1499145 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1195130 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2694275 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1499145 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47367240 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1420 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 316749 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4799333 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53983912 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096909 # Total number of read requests seen
-system.physmem.writeReqs 813132 # Total number of write requests seen
-system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966202176 # Total number of bytes read from memory
-system.physmem.bytesWritten 52040448 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129436368 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 363 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943955 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943427 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 943468 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943391 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943248 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943111 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943293 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943780 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943638 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943709 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943744 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943610 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 943654 # Track reads on a per bank basis
+system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096906 # Total number of read requests seen
+system.physmem.writeReqs 813150 # Total number of write requests seen
+system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966201984 # Total number of bytes read from memory
+system.physmem.bytesWritten 52041600 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50098 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 49973 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50033 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50667 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50819 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51122 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51107 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51166 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51028 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1156323 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2523634566000 # Total gap between requests
+system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2523628152000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154665 # Categorize read packet sizes
+system.physmem.readPktSize::6 154662 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1910341 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59114 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 14955787 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::31 31263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 46870409147 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 317530293147 # Sum of mem lat for all requests
-system.physmem.totBusLat 60386184000 # Total cycles spent in databus access
-system.physmem.totBankLat 210273700000 # Total cycles spent in bank access
-system.physmem.avgQLat 3104.71 # Average queueing delay per request
-system.physmem.avgBankLat 13928.60 # Average bank access latency per request
+system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests
+system.physmem.totBusLat 60386064000 # Total cycles spent in databus access
+system.physmem.totBankLat 210270186000 # Total cycles spent in bank access
+system.physmem.avgQLat 3102.65 # Average queueing delay per request
+system.physmem.avgBankLat 13928.39 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 21033.31 # Average memory access latency
+system.physmem.avgMemAccLat 21031.04 # Average memory access latency
system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.52 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.13 # Average read queue length over time
-system.physmem.avgWrQLen 12.37 # Average write queue length over time
-system.physmem.readRowHits 15050555 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784512 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 13.20 # Average write queue length over time
+system.physmem.readRowHits 15050623 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784578 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.48 # Row buffer hit rate for writes
-system.physmem.avgGap 158618.99 # Average gap between requests
+system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes
+system.physmem.avgGap 158618.43 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15048983 # DTB read hits
-system.cpu.checker.dtb.read_misses 7307 # DTB read misses
-system.cpu.checker.dtb.write_hits 11294245 # DTB write hits
+system.cpu.checker.dtb.read_hits 15048943 # DTB read hits
+system.cpu.checker.dtb.read_misses 7309 # DTB read misses
+system.cpu.checker.dtb.write_hits 11294215 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15056290 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11296434 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 15056252 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11296404 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26343228 # DTB hits
-system.cpu.checker.dtb.misses 9496 # DTB misses
-system.cpu.checker.dtb.accesses 26352724 # DTB accesses
-system.cpu.checker.itb.inst_hits 61776100 # ITB inst hits
+system.cpu.checker.dtb.hits 26343158 # DTB hits
+system.cpu.checker.dtb.misses 9498 # DTB misses
+system.cpu.checker.dtb.accesses 26352656 # DTB accesses
+system.cpu.checker.itb.inst_hits 61775988 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61780571 # ITB inst accesses
-system.cpu.checker.itb.hits 61776100 # DTB hits
+system.cpu.checker.itb.inst_accesses 61780459 # ITB inst accesses
+system.cpu.checker.itb.hits 61775988 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61780571 # DTB accesses
-system.cpu.checker.numCycles 78236084 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61780459 # DTB accesses
+system.cpu.checker.numCycles 78235930 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51390867 # DTB read hits
-system.cpu.dtb.read_misses 77330 # DTB read misses
-system.cpu.dtb.write_hits 11807590 # DTB write hits
-system.cpu.dtb.write_misses 17145 # DTB write misses
+system.cpu.dtb.read_hits 51393832 # DTB read hits
+system.cpu.dtb.read_misses 77273 # DTB read misses
+system.cpu.dtb.write_hits 11807513 # DTB write hits
+system.cpu.dtb.write_misses 17284 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7744 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2913 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 528 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 7715 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51468197 # DTB read accesses
-system.cpu.dtb.write_accesses 11824735 # DTB write accesses
+system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51471105 # DTB read accesses
+system.cpu.dtb.write_accesses 11824797 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63198457 # DTB hits
-system.cpu.dtb.misses 94475 # DTB misses
-system.cpu.dtb.accesses 63292932 # DTB accesses
-system.cpu.itb.inst_hits 11866859 # ITB inst hits
-system.cpu.itb.inst_misses 12387 # ITB inst misses
+system.cpu.dtb.hits 63201345 # DTB hits
+system.cpu.dtb.misses 94557 # DTB misses
+system.cpu.dtb.accesses 63295902 # DTB accesses
+system.cpu.itb.inst_hits 11866090 # ITB inst hits
+system.cpu.itb.inst_misses 12256 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5196 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5202 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3124 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11879246 # ITB inst accesses
-system.cpu.itb.hits 11866859 # DTB hits
-system.cpu.itb.misses 12387 # DTB misses
-system.cpu.itb.accesses 11879246 # DTB accesses
-system.cpu.numCycles 471620131 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11878346 # ITB inst accesses
+system.cpu.itb.hits 11866090 # DTB hits
+system.cpu.itb.misses 12256 # DTB misses
+system.cpu.itb.accesses 11878346 # DTB accesses
+system.cpu.numCycles 471617242 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14707897 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11700483 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 783548 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9751137 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7864369 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1453661 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 82859 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 30173854 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 91943847 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14707897 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9318030 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20602156 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4980521 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 134933 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 96636325 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2675 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 101652 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 208965 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11862984 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 731347 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6597 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151294412 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.758755 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.115735 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130709145 86.39% 86.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1380335 0.91% 87.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1756131 1.16% 88.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2339631 1.55% 90.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2142384 1.42% 91.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1132136 0.75% 92.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2619139 1.73% 93.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 785245 0.52% 94.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8430266 5.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151294412 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.194953 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32008731 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96268896 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18723702 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1031258 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3261825 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2020367 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 174818 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 109258714 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3261825 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33805354 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36852775 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53319596 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17901114 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6153748 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 104067610 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21499 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1015662 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4122290 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 31949 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 107816884 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 475027641 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 474936857 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90784 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78731329 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 29085554 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 891358 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 796895 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12333147 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20062338 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13521403 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1975115 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2433562 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 96511960 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2056994 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 123962105 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 189941 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 20009013 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 50083503 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 512489 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151294412 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819344 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.531574 # Number of insts issued each cycle
+system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 106913550 70.67% 70.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13863924 9.16% 79.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7098415 4.69% 84.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5869010 3.88% 88.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12472838 8.24% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2771623 1.83% 98.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1718676 1.14% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 458210 0.30% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 128166 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151294412 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 56852 0.64% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8372882 94.63% 95.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 417861 4.72% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58285332 47.02% 47.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95139 0.08% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52764596 42.57% 89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12451206 10.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 123962105 # Type of FU issued
-system.cpu.iq.rate 0.262843 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8847599 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071373 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 408327002 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 118594240 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86288141 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23234 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12518 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10286 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132433714 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12324 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 628913 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued
+system.cpu.iq.rate 0.262844 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4346263 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7649 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29949 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1722835 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107855 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 695994 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3261825 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27934565 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 435305 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 98793776 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 231675 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20062338 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13521403 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1465659 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113955 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3708 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29949 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 409673 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 293589 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 703262 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121754884 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52078341 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2207221 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions
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+system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 224822 # number of nop insts executed
-system.cpu.iew.exec_refs 64398044 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11600510 # Number of branches executed
-system.cpu.iew.exec_stores 12319703 # Number of stores executed
-system.cpu.iew.exec_rate 0.258163 # Inst execution rate
-system.cpu.iew.wb_sent 120731241 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86298427 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47352499 # num instructions producing a value
-system.cpu.iew.wb_consumers 88423671 # num instructions consuming a value
+system.cpu.iew.exec_nop 224578 # number of nop insts executed
+system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed
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+system.cpu.iew.exec_rate 0.258166 # Inst execution rate
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+system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182983 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535518 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 19868331 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544505 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 611839 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::mean 0.527265 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120340532 81.25% 81.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13566988 9.16% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3964696 2.68% 93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2137699 1.44% 94.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1955021 1.32% 95.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 974024 0.66% 96.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1590640 1.07% 97.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 730936 0.49% 98.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2854479 1.93% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 148115015 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60747728 # Number of instructions committed
-system.cpu.commit.committedOps 78095905 # Number of ops (including micro ops) committed
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+system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69134339 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995983 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2854479 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69134185 # Number of committed integer instructions.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.rob.rob_writes 199282329 # The number of ROB writes
-system.cpu.timesIdled 1774359 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320325719 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4575563546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60597347 # Number of Instructions Simulated
-system.cpu.committedOps 77945524 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60597347 # Number of Instructions Simulated
-system.cpu.cpi 7.782851 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.782851 # CPI: Total CPI of All Threads
+system.cpu.rob.rob_reads 241297904 # The number of ROB reads
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+system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60597236 # Number of Instructions Simulated
+system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated
+system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads
system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 551501620 # number of integer regfile reads
-system.cpu.int_regfile_writes 88408652 # number of integer regfile writes
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system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7052500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7052500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7052500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 7052500 # number of overall MSHR uncacheable cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11567.158784 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.dcache.tagsinuse 511.994184 # Cycle average of tags in use
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system.cpu.dcache.warmup_cycle 35202000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026721 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015554 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982251 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982251 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540955 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540955 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222853 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.090296 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000672 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222846 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.090299 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222853 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.090296 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222846 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.090299 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40979.476225 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42280.789844 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41609.810573 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.448382 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.448382 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41162.338968 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42221.082084 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41688.751819 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.258098 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.258098 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37908.793347 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37908.793347 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37865.660886 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37865.660886 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1068189786972 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1068189786972 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88028 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.003417 # Number of seconds simulated
-sim_ticks 1003417221500 # Number of ticks simulated
-final_tick 1003417221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.603317 # Number of seconds simulated
+sim_ticks 2603316759000 # Number of ticks simulated
+final_tick 2603316759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74785 # Simulator instruction rate (inst/s)
-host_op_rate 96230 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1214309093 # Simulator tick rate (ticks/s)
-host_mem_usage 406952 # Number of bytes of host memory used
-host_seconds 826.33 # Real time elapsed on the host
-sim_insts 61797296 # Number of instructions simulated
-sim_ops 79517775 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory
+host_inst_rate 64170 # Simulator instruction rate (inst/s)
+host_op_rate 82590 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2648964509 # Simulator tick rate (ticks/s)
+host_mem_usage 407980 # Number of bytes of host memory used
+host_seconds 982.77 # Real time elapsed on the host
+sim_insts 63063787 # Number of instructions simulated
+sim_ops 81167171 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 410432 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4376692 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 404672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5217200 # Number of bytes read from this memory
-system.physmem.bytes_read::total 54451236 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 410432 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 404672 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4253056 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 396352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4375860 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 425408 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5260720 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131570852 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 396352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 425408 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4284288 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7280144 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7313424 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6413 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68458 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6323 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 81545 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5667795 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66454 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6193 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68445 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6647 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 82225 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15302357 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66942 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 823226 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43890209 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 957 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 128 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 409034 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 4361787 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 957 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 403294 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 5199432 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 54265798 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 409034 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 403294 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 812328 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4238572 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 16942 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2999837 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 7255351 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4238572 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43890209 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 128 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 409034 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 4378729 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 403294 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 8199269 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 61521149 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5667795 # Total number of read requests seen
-system.physmem.writeReqs 823226 # Total number of write requests seen
-system.physmem.cpureqs 281286 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 362738880 # Total number of bytes read from memory
-system.physmem.bytesWritten 52686464 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 54451236 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7280144 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 148 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 12596 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 354151 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 354519 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 354412 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 354404 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 354227 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 354027 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 353803 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 353914 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 354718 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 354198 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 354245 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 354391 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 354136 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 354309 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 354144 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 354049 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50660 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50996 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50931 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50952 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51753 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51624 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51424 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51487 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51960 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51682 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51566 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51627 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51620 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51624 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51572 # Track writes on a per bank basis
+system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 824226 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46521626 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 320 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 152249 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1680879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 163410 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2020776 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50539702 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 152249 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 163410 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315659 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1645704 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 1157038 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2809272 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1645704 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46521626 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 320 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 152249 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1687409 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 163410 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 3177814 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53348973 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15302357 # Total number of read requests seen
+system.physmem.writeReqs 824226 # Total number of write requests seen
+system.physmem.cpureqs 284853 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 979350848 # Total number of bytes read from memory
+system.physmem.bytesWritten 52750464 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 131570852 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7313424 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 375 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 14171 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 956419 # Track reads on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1152068 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1003416092000 # Total gap between requests
+system.physmem.numWrRetry 1152088 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2603315545500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
-system.physmem.readPktSize::3 5505024 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 46980948909 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 148397952909 # Sum of mem lat for all requests
-system.physmem.totBusLat 22670588000 # Total cycles spent in databus access
-system.physmem.totBankLat 78746416000 # Total cycles spent in bank access
-system.physmem.avgQLat 8289.32 # Average queueing delay per request
-system.physmem.avgBankLat 13894.02 # Average bank access latency per request
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+system.physmem.totBusLat 61207928000 # Total cycles spent in databus access
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+system.physmem.avgBankLat 13929.10 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26183.34 # Average memory access latency
-system.physmem.avgRdBW 361.50 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 52.51 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 54.27 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 7.26 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 21069.98 # Average memory access latency
+system.physmem.avgRdBW 376.19 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.59 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 11.87 # Average write queue length over time
-system.physmem.readRowHits 5638305 # Number of row buffer hits during reads
-system.physmem.writeRowHits 788804 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 95.82 # Row buffer hit rate for writes
-system.physmem.avgGap 154585.25 # Average gap between requests
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system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
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-system.realview.nvmem.bw_read::cpu1.inst 383 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 446 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 64 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 383 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 446 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 64 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 383 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 446 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 72379 # number of replacements
-system.l2c.tagsinuse 54036.280833 # Cycle average of tags in use
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-system.l2c.sampled_refs 137571 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.707060 # Average number of references to valid blocks.
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+system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
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+system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 73153 # number of replacements
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+system.l2c.avg_refs 13.895477 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.Writeback_hits::total 582352 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 1132 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 800 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1932 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 336 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 48068 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 59137 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 107205 # number of ReadExReq hits
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-system.l2c.overall_hits::total 1554438 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 15 # number of ReadReq misses
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system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2140 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 358 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 2158 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1224 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 336 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9026340 # DTB read accesses
-system.cpu0.dtb.write_accesses 5203289 # DTB write accesses
+system.cpu0.dtb.perms_faults 569 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 9099765 # DTB read accesses
+system.cpu0.dtb.write_accesses 5287133 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14187570 # DTB hits
-system.cpu0.dtb.misses 42059 # DTB misses
-system.cpu0.dtb.accesses 14229629 # DTB accesses
-system.cpu0.itb.inst_hits 4354083 # ITB inst hits
-system.cpu0.itb.inst_misses 5531 # ITB inst misses
+system.cpu0.dtb.hits 14344198 # DTB hits
+system.cpu0.dtb.misses 42700 # DTB misses
+system.cpu0.dtb.accesses 14386898 # DTB accesses
+system.cpu0.itb.inst_hits 4425189 # ITB inst hits
+system.cpu0.itb.inst_misses 5562 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1363 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1395 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4359614 # ITB inst accesses
-system.cpu0.itb.hits 4354083 # DTB hits
-system.cpu0.itb.misses 5531 # DTB misses
-system.cpu0.itb.accesses 4359614 # DTB accesses
-system.cpu0.numCycles 68779590 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4430751 # ITB inst accesses
+system.cpu0.itb.hits 4425189 # DTB hits
+system.cpu0.itb.misses 5562 # DTB misses
+system.cpu0.itb.accesses 4430751 # DTB accesses
+system.cpu0.numCycles 69436793 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 6151354 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 4687077 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 326469 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 3738602 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 3006788 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 6232893 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 4743306 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 327822 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 3788300 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 3047807 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 689169 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 32083 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 11912972 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 32706056 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6151354 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3695957 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7689921 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1565411 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 62995 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 21287015 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 56402 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4352320 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 172729 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2628 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 42226826 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.000152 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.378860 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 701189 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 31986 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 12165372 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 33223009 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6232893 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3748996 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7801748 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1579515 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 70495 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 21773574 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 5807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 55458 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 92257 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4423471 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 173760 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2652 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 43098147 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.994806 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.374305 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 34545116 81.81% 81.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 600326 1.42% 83.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 813270 1.93% 85.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 699242 1.66% 86.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 789636 1.87% 88.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 563805 1.34% 90.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 711205 1.68% 91.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 369975 0.88% 92.58% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3134251 7.42% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 35304381 81.92% 81.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 609582 1.41% 83.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 823952 1.91% 85.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 710643 1.65% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 795409 1.85% 88.74% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 570879 1.32% 90.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 720960 1.67% 91.73% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 375620 0.87% 92.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3186721 7.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 42226826 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.089436 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.475520 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12413850 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 21262916 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6920770 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 571279 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1058011 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 957289 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 65649 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 40810463 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 214284 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1058011 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12995838 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5806909 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13316140 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6858946 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2190982 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 39610027 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2116 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 435032 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1231897 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 105 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 39982485 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 178864927 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 178830724 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34203 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 31105315 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8877169 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 451261 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 410052 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5376793 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7771036 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5796008 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1117778 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1234382 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 37385936 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 932152 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37680469 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 87348 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6705798 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 14225412 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 253293 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 42226826 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.892335 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 43098147 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.089764 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.478464 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12694368 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 21733151 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 7021973 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 580158 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1068497 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 974425 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 66014 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 41440720 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 216131 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1068497 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 13283568 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5811502 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13763022 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6961604 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2209954 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 40230567 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 2204 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 441496 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1232571 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 70 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 40628697 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 181762207 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 181727693 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34514 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 31673882 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8954814 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 460934 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 417253 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5454618 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7893877 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5899231 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1129288 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1250491 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 37987189 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 942287 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 38211306 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 88088 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6766776 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 14417426 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 253739 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 43098147 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.886611 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.498890 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 26789201 63.44% 63.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5974229 14.15% 77.59% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3183905 7.54% 85.13% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2487856 5.89% 91.02% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2118052 5.02% 96.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 933005 2.21% 98.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 499456 1.18% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 188083 0.45% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 53039 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 27429044 63.64% 63.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 6069688 14.08% 77.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3249267 7.54% 85.27% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2519397 5.85% 91.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2120550 4.92% 96.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 959758 2.23% 98.26% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 504062 1.17% 99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 191517 0.44% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 54864 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 42226826 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 43098147 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 25386 2.38% 2.38% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 456 0.04% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 25519 2.38% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 464 0.04% 2.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 843676 78.98% 81.40% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 198710 18.60% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 839951 78.37% 80.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 205830 19.20% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22597326 59.97% 60.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 48684 0.13% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9468734 25.13% 85.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5512785 14.63% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 52084 0.14% 0.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22953142 60.07% 60.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 49969 0.13% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 683 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9542960 24.97% 85.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5612439 14.69% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37680469 # Type of FU issued
-system.cpu0.iq.rate 0.547844 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1068228 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028350 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 118776881 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 45031578 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 34706639 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8278 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4652 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38692178 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4305 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 310856 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 38211306 # Type of FU issued
+system.cpu0.iq.rate 0.550303 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1071764 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028048 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 120714498 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 45704259 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 35275992 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8506 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4731 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3909 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 39226540 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4446 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 323503 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1466992 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3639 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 12971 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 614314 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1474665 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3677 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13402 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 626328 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2192663 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5266 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2149439 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1058011 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4168228 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 100403 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 38437075 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 94997 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7771036 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5796008 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 609484 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 39021 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3188 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 12971 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 173285 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 127529 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 300814 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 37265519 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9306913 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 414950 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1068497 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4177933 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 101495 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 39049116 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 95858 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7893877 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5899231 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 616112 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 40709 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 3360 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13402 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 173604 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 128122 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 301726 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 37794024 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9381421 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 417282 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 118987 # number of nop insts executed
-system.cpu0.iew.exec_refs 14762216 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4927541 # Number of branches executed
-system.cpu0.iew.exec_stores 5455303 # Number of stores executed
-system.cpu0.iew.exec_rate 0.541811 # Inst execution rate
-system.cpu0.iew.wb_sent 37049261 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 34710512 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18431396 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35371181 # num instructions consuming a value
+system.cpu0.iew.exec_nop 119640 # number of nop insts executed
+system.cpu0.iew.exec_refs 14935051 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4997979 # Number of branches executed
+system.cpu0.iew.exec_stores 5553630 # Number of stores executed
+system.cpu0.iew.exec_rate 0.544294 # Inst execution rate
+system.cpu0.iew.wb_sent 37576425 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 35279901 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18742857 # num instructions producing a value
+system.cpu0.iew.wb_consumers 36023721 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.504663 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.521085 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.508087 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.520292 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6565608 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 678859 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 262014 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 41204670 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.762989 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.718954 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6624150 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 688548 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 263048 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 42066039 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.760422 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.715065 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 29337596 71.20% 71.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5890386 14.30% 85.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1942613 4.71% 90.21% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 987342 2.40% 92.61% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 788686 1.91% 94.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 508616 1.23% 95.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 388471 0.94% 96.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 215239 0.52% 97.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1145721 2.78% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 29990291 71.29% 71.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5984334 14.23% 85.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1979513 4.71% 90.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1007903 2.40% 92.62% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 802639 1.91% 94.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 528288 1.26% 95.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 397543 0.95% 96.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 220589 0.52% 97.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1154939 2.75% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 41204670 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 23832067 # Number of instructions committed
-system.cpu0.commit.committedOps 31438729 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 42066039 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 24262669 # Number of instructions committed
+system.cpu0.commit.committedOps 31987958 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11485738 # Number of memory references committed
-system.cpu0.commit.loads 6304044 # Number of loads committed
-system.cpu0.commit.membars 231899 # Number of memory barriers committed
-system.cpu0.commit.branches 4278221 # Number of branches committed
+system.cpu0.commit.refs 11692115 # Number of memory references committed
+system.cpu0.commit.loads 6419212 # Number of loads committed
+system.cpu0.commit.membars 234468 # Number of memory barriers committed
+system.cpu0.commit.branches 4346825 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 27759030 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 489603 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1145721 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 28256367 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 500017 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1154939 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 77195085 # The number of ROB reads
-system.cpu0.rob.rob_writes 77069186 # The number of ROB writes
-system.cpu0.timesIdled 361877 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26552764 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 1938011770 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 23751325 # Number of Instructions Simulated
-system.cpu0.committedOps 31357987 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 23751325 # Number of Instructions Simulated
-system.cpu0.cpi 2.895821 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.895821 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.345325 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.345325 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 173747096 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34492759 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3279 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 922 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 46707854 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 520465 # number of misc regfile writes
-system.cpu0.icache.replacements 396840 # number of replacements
-system.cpu0.icache.tagsinuse 510.969252 # Cycle average of tags in use
-system.cpu0.icache.total_refs 3922693 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 397352 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 9.872086 # Average number of references to valid blocks.
+system.cpu0.rob.rob_reads 78638973 # The number of ROB reads
+system.cpu0.rob.rob_writes 78294863 # The number of ROB writes
+system.cpu0.timesIdled 365151 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 26338646 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5137152930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 24181927 # Number of Instructions Simulated
+system.cpu0.committedOps 31907216 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 24181927 # Number of Instructions Simulated
+system.cpu0.cpi 2.871433 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.871433 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.348258 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.348258 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 176324047 # number of integer regfile reads
+system.cpu0.int_regfile_writes 35061690 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 912 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 47470625 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 527597 # number of misc regfile writes
+system.cpu0.icache.replacements 404775 # number of replacements
+system.cpu0.icache.tagsinuse 511.602715 # Cycle average of tags in use
+system.cpu0.icache.total_refs 3985323 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 405287 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 9.833335 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 510.969252 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.997987 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.997987 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3922693 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3922693 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3922693 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3922693 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3922693 # number of overall hits
-system.cpu0.icache.overall_hits::total 3922693 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 429491 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 429491 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 429491 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 429491 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 429491 # number of overall misses
-system.cpu0.icache.overall_misses::total 429491 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5849216498 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5849216498 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5849216498 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5849216498 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5849216498 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5849216498 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 4352184 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 4352184 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 4352184 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 4352184 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 4352184 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 4352184 # number of overall (read+write) accesses
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+system.cpu0.dcache.overall_misses::total 1971248 # number of overall misses
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+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50615000 # number of StoreCondReq miss cycles
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+system.cpu0.dcache.overall_miss_latency::total 66759817368 # number of overall miss cycles
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+system.cpu0.dcache.demand_accesses::total 11138509 # number of demand (read+write) accesses
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+system.cpu0.dcache.overall_accesses::total 11138509 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061744 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.061744 # miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::total 0.328177 # miss rate for WriteReq accesses
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+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048610 # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043253 # miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_miss_rate::total 0.176976 # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::total 0.176976 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13753.886183 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13753.886183 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38832.080526 # average WriteReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9895.933955 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6525.915420 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6525.915420 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33866.777477 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33866.777477 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 7897 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 2466 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 585 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 72 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.499145 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 34.250000 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 256407 # number of writebacks
-system.cpu0.dcache.writebacks::total 256407 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200970 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 200970 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450977 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1450977 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.demand_mshr_hits::total 1651947 # number of demand (read+write) MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::total 1651947 # number of overall MSHR hits
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-system.cpu0.dcache.ReadReq_mshr_misses::total 188383 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130394 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 130394 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8358 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8358 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7458 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7458 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.demand_mshr_misses::total 318777 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 318777 # number of overall MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2337539000 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66744000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66744000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31921000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6366935491 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total 6366935491 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13497539000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13497539000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1126787391 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1126787391 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14624326391 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14624326391 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030296 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030296 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027498 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027498 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045785 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045785 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041703 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041703 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029086 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.029086 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12408.439190 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12408.439190 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30901.701696 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30901.701696 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7985.642498 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7985.642498 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4280.101904 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4280.101904 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 255626 # number of writebacks
+system.cpu0.dcache.writebacks::total 255626 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201523 # number of ReadReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 1651307 # number of overall MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8435 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2338858500 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431962000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431962000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199718891 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199718891 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631680891 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029863 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029863 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027229 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027229 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046054 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046054 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043247 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043247 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12389.990465 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12389.990465 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31163.545990 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31163.545990 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7872.969769 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7872.969769 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4527.014829 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4527.014829 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 42793425 # DTB read hits
-system.cpu1.dtb.read_misses 43166 # DTB read misses
-system.cpu1.dtb.write_hits 6855715 # DTB write hits
-system.cpu1.dtb.write_misses 11673 # DTB write misses
+system.cpu1.dtb.read_hits 43093620 # DTB read hits
+system.cpu1.dtb.read_misses 44212 # DTB read misses
+system.cpu1.dtb.write_hits 7019560 # DTB write hits
+system.cpu1.dtb.write_misses 11765 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 3409 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 352 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 3591 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 42836591 # DTB read accesses
-system.cpu1.dtb.write_accesses 6867388 # DTB write accesses
+system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 43137832 # DTB read accesses
+system.cpu1.dtb.write_accesses 7031325 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 49649140 # DTB hits
-system.cpu1.dtb.misses 54839 # DTB misses
-system.cpu1.dtb.accesses 49703979 # DTB accesses
-system.cpu1.itb.inst_hits 7790428 # ITB inst hits
-system.cpu1.itb.inst_misses 6195 # ITB inst misses
+system.cpu1.dtb.hits 50113180 # DTB hits
+system.cpu1.dtb.misses 55977 # DTB misses
+system.cpu1.dtb.accesses 50169157 # DTB accesses
+system.cpu1.itb.inst_hits 7945263 # ITB inst hits
+system.cpu1.itb.inst_misses 6054 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1551 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1580 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1608 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1618 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7796623 # ITB inst accesses
-system.cpu1.itb.hits 7790428 # DTB hits
-system.cpu1.itb.misses 6195 # DTB misses
-system.cpu1.itb.accesses 7796623 # DTB accesses
-system.cpu1.numCycles 407481845 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7951317 # ITB inst accesses
+system.cpu1.itb.hits 7945263 # DTB hits
+system.cpu1.itb.misses 6054 # DTB misses
+system.cpu1.itb.accesses 7951317 # DTB accesses
+system.cpu1.numCycles 409430571 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 8945563 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 7276620 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 457303 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 6059330 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 5044901 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 9152257 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 7432560 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 466867 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 6195424 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 5148293 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 808900 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 49599 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 19209398 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 61160390 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 8945563 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 5853801 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 13372143 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3528800 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 72716 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 77592776 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 4530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 48363 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 137630 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 7788411 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 558980 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3579 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 112853111 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.663918 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.993452 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 835215 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 50625 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 19713770 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 62254744 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9152257 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5983508 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 13632356 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3573599 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 74747 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 78115877 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 5836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 48120 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 142516 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 7943235 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 563949 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3459 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 114180028 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.668662 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.999663 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 99488795 88.16% 88.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 820731 0.73% 88.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 982302 0.87% 89.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1718236 1.52% 91.28% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1416689 1.26% 92.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 588425 0.52% 93.05% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1946926 1.73% 94.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 433337 0.38% 95.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5457670 4.84% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 100555609 88.07% 88.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 838988 0.73% 88.80% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 1011000 0.89% 89.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1744900 1.53% 91.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1443541 1.26% 92.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 605100 0.53% 93.01% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1974563 1.73% 94.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 445551 0.39% 95.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5560776 4.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 112853111 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.021953 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.150094 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 20594111 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 77223821 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12189210 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 529456 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2316513 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1140486 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 100773 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 70872122 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 333080 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2316513 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 21811188 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 31999564 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 40913868 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11406608 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4405370 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 66851676 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 19516 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 679552 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3147713 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 33677 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 70148588 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 306845192 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 306785894 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 59298 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 49106817 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 21041771 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 463027 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 405725 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 7962793 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 12778752 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8032472 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1035556 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1464082 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 61394803 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1176532 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 88185041 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 108507 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 14048968 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 37726295 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 276552 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 112853111 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.781414 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.519020 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 114180028 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022354 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.152052 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 21120325 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 77740288 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 12430171 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 543608 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2345636 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1176073 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 102892 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 72257305 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 341492 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2345636 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 22356190 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 32102348 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 41268894 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11643477 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4463483 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 68190005 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 19565 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 695237 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3171764 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 33722 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 71496605 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 312933263 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 312874076 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59187 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 50205657 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 21290948 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 480351 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 419670 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 8129610 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 13049293 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8227563 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1078580 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1518105 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 62664777 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1204533 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 89464326 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 109059 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 14241211 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 38124625 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 284346 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 114180028 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.783537 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.520062 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 82669825 73.25% 73.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8481760 7.52% 80.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4273659 3.79% 84.56% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3671895 3.25% 87.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10427666 9.24% 97.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1949609 1.73% 98.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1042899 0.92% 99.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 262209 0.23% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 73589 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 83489742 73.12% 73.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8670086 7.59% 80.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4385231 3.84% 84.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3749968 3.28% 87.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10493751 9.19% 97.03% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1975559 1.73% 98.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1067200 0.93% 99.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 270053 0.24% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 78438 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 112853111 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 114180028 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 26972 0.34% 0.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 996 0.01% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7550123 96.09% 96.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 279583 3.56% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 28685 0.36% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 990 0.01% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7576734 95.92% 96.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 292663 3.71% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 36904735 41.85% 42.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59478 0.07% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1462 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43687858 49.54% 91.82% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7217483 8.18% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 37676817 42.11% 42.46% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 61442 0.07% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 44006207 49.19% 91.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7404070 8.28% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 88185041 # Type of FU issued
-system.cpu1.iq.rate 0.216415 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7857674 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.089104 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 297228981 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 76628774 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 53465228 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 15030 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8076 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6856 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 95720841 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7877 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 343881 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 89464326 # Type of FU issued
+system.cpu1.iq.rate 0.218509 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7899072 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.088293 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 301157769 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 78119517 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 54662771 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 14827 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8100 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 97041573 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7763 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 356788 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 3018668 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 4236 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17116 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1176826 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 3051550 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 4387 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17666 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1202172 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31906521 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 692078 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31965367 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 692896 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2316513 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24121346 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 362647 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 62677152 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 130612 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 12778752 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8032472 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 873727 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 64946 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17116 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 239035 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 168853 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 407888 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 86386034 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43162344 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1799007 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2345636 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24201399 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 366318 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 63975423 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 133542 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 13049293 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8227563 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 893848 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 67557 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17666 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 244185 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 171619 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 415804 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 87650825 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43476570 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1813501 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 105817 # number of nop insts executed
-system.cpu1.iew.exec_refs 50303914 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6949979 # Number of branches executed
-system.cpu1.iew.exec_stores 7141570 # Number of stores executed
-system.cpu1.iew.exec_rate 0.212000 # Inst execution rate
-system.cpu1.iew.wb_sent 85560494 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 53472084 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 29815301 # num instructions producing a value
-system.cpu1.iew.wb_consumers 53181116 # num instructions consuming a value
+system.cpu1.iew.exec_nop 106113 # number of nop insts executed
+system.cpu1.iew.exec_refs 50801692 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 7123929 # Number of branches executed
+system.cpu1.iew.exec_stores 7325122 # Number of stores executed
+system.cpu1.iew.exec_rate 0.214080 # Inst execution rate
+system.cpu1.iew.wb_sent 86821194 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 54669578 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 30455976 # num instructions producing a value
+system.cpu1.iew.wb_consumers 54432612 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.131226 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.560637 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.133526 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.559517 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 14046998 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 899980 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 358444 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 110583599 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.436135 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.404322 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 14216299 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 920187 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 365862 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 111882823 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.440904 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.409715 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 93772628 84.80% 84.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8260056 7.47% 92.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2160964 1.95% 94.22% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1246626 1.13% 95.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1244768 1.13% 96.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 580382 0.52% 97.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 994186 0.90% 97.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 530445 0.48% 98.38% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1793544 1.62% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 94662436 84.61% 84.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8450873 7.55% 92.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2228797 1.99% 94.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1285384 1.15% 95.30% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1281795 1.15% 96.45% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 596967 0.53% 96.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1010034 0.90% 97.88% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 539540 0.48% 98.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1826997 1.63% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 110583599 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38115610 # Number of instructions committed
-system.cpu1.commit.committedOps 48229427 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 111882823 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38951499 # Number of instructions committed
+system.cpu1.commit.committedOps 49329594 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16615730 # Number of memory references committed
-system.cpu1.commit.loads 9760084 # Number of loads committed
-system.cpu1.commit.membars 196512 # Number of memory barriers committed
-system.cpu1.commit.branches 5981373 # Number of branches committed
-system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 42745221 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 536771 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1793544 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 17023134 # Number of memory references committed
+system.cpu1.commit.loads 9997743 # Number of loads committed
+system.cpu1.commit.membars 202380 # Number of memory barriers committed
+system.cpu1.commit.branches 6138522 # Number of branches committed
+system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 43719778 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 556453 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1826997 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 169976861 # The number of ROB reads
-system.cpu1.rob.rob_writes 126957772 # The number of ROB writes
-system.cpu1.timesIdled 1410203 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 294628734 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 1598708296 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 38045971 # Number of Instructions Simulated
-system.cpu1.committedOps 48159788 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 38045971 # Number of Instructions Simulated
-system.cpu1.cpi 10.710250 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.710250 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.093369 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.093369 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 386616069 # number of integer regfile reads
-system.cpu1.int_regfile_writes 55621377 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 5021 # number of floating regfile reads
+system.cpu1.rob.rob_reads 172487010 # The number of ROB reads
+system.cpu1.rob.rob_writes 129525616 # The number of ROB writes
+system.cpu1.timesIdled 1423460 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 295250543 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 4796554837 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 38881860 # Number of Instructions Simulated
+system.cpu1.committedOps 49259955 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 38881860 # Number of Instructions Simulated
+system.cpu1.cpi 10.530118 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 10.530118 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.094966 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.094966 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 392568937 # number of integer regfile reads
+system.cpu1.int_regfile_writes 56802865 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 4926 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 80414047 # number of misc regfile reads
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-system.cpu1.dcache.demand_avg_miss_latency::total 35807.969932 # average overall miss latency
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12385.472390 # average ReadReq mshr miss latency
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+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3377.383572 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 421898642152 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 421898642152 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 421898642152 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 421898642152 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1082331782222 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1082331782222 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 43084 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 43796 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 52242 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.523636 # Number of seconds simulated
-sim_ticks 2523635852000 # Number of ticks simulated
-final_tick 2523635852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.523629 # Number of seconds simulated
+sim_ticks 2523629285500 # Number of ticks simulated
+final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 45530 # Simulator instruction rate (inst/s)
-host_op_rate 58565 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1896155435 # Simulator tick rate (ticks/s)
-host_mem_usage 399768 # Number of bytes of host memory used
-host_seconds 1330.92 # Real time elapsed on the host
-sim_insts 60597347 # Number of instructions simulated
-sim_ops 77945524 # Number of ops (including micro ops) simulated
+host_inst_rate 77702 # Simulator instruction rate (inst/s)
+host_op_rate 99947 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3235958193 # Simulator tick rate (ticks/s)
+host_mem_usage 399788 # Number of bytes of host memory used
+host_seconds 779.87 # Real time elapsed on the host
+sim_insts 60597236 # Number of instructions simulated
+sim_ops 77945371 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 799360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129436368 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 799360 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 799360 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory
+system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 56 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12490 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096909 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47367240 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1420 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 316749 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3604203 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51289637 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 316749 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316749 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1499145 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1195130 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2694275 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1499145 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47367240 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1420 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 316749 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4799333 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53983912 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096909 # Total number of read requests seen
-system.physmem.writeReqs 813132 # Total number of write requests seen
-system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966202176 # Total number of bytes read from memory
-system.physmem.bytesWritten 52040448 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129436368 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 363 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943955 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943427 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 943468 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943391 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943248 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943111 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943293 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943780 # Track reads on a per bank basis
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+system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096906 # Total number of read requests seen
+system.physmem.writeReqs 813150 # Total number of write requests seen
+system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966201984 # Total number of bytes read from memory
+system.physmem.bytesWritten 52041600 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed
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system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::11 51107 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::15 51028 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1156323 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2523634566000 # Total gap between requests
+system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2523628152000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154665 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1910341 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59114 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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-system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31424 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 46870409147 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 317530293147 # Sum of mem lat for all requests
-system.physmem.totBusLat 60386184000 # Total cycles spent in databus access
-system.physmem.totBankLat 210273700000 # Total cycles spent in bank access
-system.physmem.avgQLat 3104.71 # Average queueing delay per request
-system.physmem.avgBankLat 13928.60 # Average bank access latency per request
+system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests
+system.physmem.totBusLat 60386064000 # Total cycles spent in databus access
+system.physmem.totBankLat 210270186000 # Total cycles spent in bank access
+system.physmem.avgQLat 3102.65 # Average queueing delay per request
+system.physmem.avgBankLat 13928.39 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 21033.31 # Average memory access latency
+system.physmem.avgMemAccLat 21031.04 # Average memory access latency
system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.52 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.13 # Average read queue length over time
-system.physmem.avgWrQLen 12.37 # Average write queue length over time
-system.physmem.readRowHits 15050555 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784512 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 13.20 # Average write queue length over time
+system.physmem.readRowHits 15050623 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784578 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.48 # Row buffer hit rate for writes
-system.physmem.avgGap 158618.99 # Average gap between requests
+system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes
+system.physmem.avgGap 158618.43 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51390867 # DTB read hits
-system.cpu.dtb.read_misses 77330 # DTB read misses
-system.cpu.dtb.write_hits 11807590 # DTB write hits
-system.cpu.dtb.write_misses 17145 # DTB write misses
+system.cpu.dtb.read_hits 51393832 # DTB read hits
+system.cpu.dtb.read_misses 77273 # DTB read misses
+system.cpu.dtb.write_hits 11807513 # DTB write hits
+system.cpu.dtb.write_misses 17284 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4249 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2913 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 528 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4230 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51468197 # DTB read accesses
-system.cpu.dtb.write_accesses 11824735 # DTB write accesses
+system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51471105 # DTB read accesses
+system.cpu.dtb.write_accesses 11824797 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63198457 # DTB hits
-system.cpu.dtb.misses 94475 # DTB misses
-system.cpu.dtb.accesses 63292932 # DTB accesses
-system.cpu.itb.inst_hits 11866859 # ITB inst hits
-system.cpu.itb.inst_misses 12387 # ITB inst misses
+system.cpu.dtb.hits 63201345 # DTB hits
+system.cpu.dtb.misses 94557 # DTB misses
+system.cpu.dtb.accesses 63295902 # DTB accesses
+system.cpu.itb.inst_hits 11866090 # ITB inst hits
+system.cpu.itb.inst_misses 12256 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2600 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2603 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3124 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11879246 # ITB inst accesses
-system.cpu.itb.hits 11866859 # DTB hits
-system.cpu.itb.misses 12387 # DTB misses
-system.cpu.itb.accesses 11879246 # DTB accesses
-system.cpu.numCycles 471620131 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11878346 # ITB inst accesses
+system.cpu.itb.hits 11866090 # DTB hits
+system.cpu.itb.misses 12256 # DTB misses
+system.cpu.itb.accesses 11878346 # DTB accesses
+system.cpu.numCycles 471617242 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14707897 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11700483 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 783548 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9751137 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7864369 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1453661 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 82859 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 30173854 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 91943847 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14707897 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9318030 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20602156 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4980521 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 134933 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 96636325 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2675 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 101652 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 208965 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11862984 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 731347 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6597 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151294412 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.758755 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.115735 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130709145 86.39% 86.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1380335 0.91% 87.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1756131 1.16% 88.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2339631 1.55% 90.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2142384 1.42% 91.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1132136 0.75% 92.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2619139 1.73% 93.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 785245 0.52% 94.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8430266 5.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151294412 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.194953 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32008731 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96268896 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18723702 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1031258 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3261825 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2020367 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 174818 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 109258714 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3261825 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33805354 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36852775 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53319596 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17901114 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6153748 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 104067610 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21499 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1015662 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4122290 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 31949 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 107816884 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 475027641 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 474936857 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90784 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78731329 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 29085554 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 891358 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 796895 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12333147 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20062338 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13521403 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1975115 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2433562 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 96511960 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2056994 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 123962105 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 189941 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 20009013 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 50083503 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 512489 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151294412 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819344 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.531574 # Number of insts issued each cycle
+system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 106913550 70.67% 70.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13863924 9.16% 79.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7098415 4.69% 84.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5869010 3.88% 88.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12472838 8.24% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2771623 1.83% 98.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1718676 1.14% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 458210 0.30% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 128166 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151294412 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 56852 0.64% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8372882 94.63% 95.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 417861 4.72% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58285332 47.02% 47.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95139 0.08% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52764596 42.57% 89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12451206 10.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 123962105 # Type of FU issued
-system.cpu.iq.rate 0.262843 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8847599 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071373 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 408327002 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 118594240 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86288141 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23234 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12518 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10286 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132433714 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12324 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 628913 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued
+system.cpu.iq.rate 0.262844 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4346263 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7649 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29949 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1722835 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107855 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 695994 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3261825 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27934565 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 435305 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 98793776 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 231675 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20062338 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13521403 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1465659 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113955 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3708 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29949 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 409673 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 293589 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 703262 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121754884 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52078341 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2207221 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 224822 # number of nop insts executed
-system.cpu.iew.exec_refs 64398044 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11600510 # Number of branches executed
-system.cpu.iew.exec_stores 12319703 # Number of stores executed
-system.cpu.iew.exec_rate 0.258163 # Inst execution rate
-system.cpu.iew.wb_sent 120731241 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86298427 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47352499 # num instructions producing a value
-system.cpu.iew.wb_consumers 88423671 # num instructions consuming a value
+system.cpu.iew.exec_nop 224578 # number of nop insts executed
+system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11599904 # Number of branches executed
+system.cpu.iew.exec_stores 12319473 # Number of stores executed
+system.cpu.iew.exec_rate 0.258166 # Inst execution rate
+system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47354389 # num instructions producing a value
+system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182983 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535518 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 19868331 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544505 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 611839 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 148115015 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.527265 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.512607 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120340532 81.25% 81.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13566988 9.16% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3964696 2.68% 93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2137699 1.44% 94.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1955021 1.32% 95.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 974024 0.66% 96.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1590640 1.07% 97.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 730936 0.49% 98.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2854479 1.93% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 148115015 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60747728 # Number of instructions committed
-system.cpu.commit.committedOps 78095905 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60747617 # Number of instructions committed
+system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27514643 # Number of memory references committed
-system.cpu.commit.loads 15716075 # Number of loads committed
-system.cpu.commit.membars 413107 # Number of memory barriers committed
-system.cpu.commit.branches 10023098 # Number of branches committed
+system.cpu.commit.refs 27514573 # Number of memory references committed
+system.cpu.commit.loads 15716037 # Number of loads committed
+system.cpu.commit.membars 413105 # Number of memory barriers committed
+system.cpu.commit.branches 10023091 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69134339 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995983 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2854479 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69134185 # Number of committed integer instructions.
+system.cpu.commit.function_calls 995980 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 241309637 # The number of ROB reads
-system.cpu.rob.rob_writes 199282329 # The number of ROB writes
-system.cpu.timesIdled 1774359 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320325719 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4575563546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60597347 # Number of Instructions Simulated
-system.cpu.committedOps 77945524 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60597347 # Number of Instructions Simulated
-system.cpu.cpi 7.782851 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.782851 # CPI: Total CPI of All Threads
+system.cpu.rob.rob_reads 241297904 # The number of ROB reads
+system.cpu.rob.rob_writes 199283253 # The number of ROB writes
+system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60597236 # Number of Instructions Simulated
+system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated
+system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads
system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 551501617 # number of integer regfile reads
-system.cpu.int_regfile_writes 88408651 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8346 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
-system.cpu.misc_regfile_reads 124084349 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912885 # number of misc regfile writes
-system.cpu.icache.replacements 990639 # number of replacements
-system.cpu.icache.tagsinuse 510.412932 # Cycle average of tags in use
-system.cpu.icache.total_refs 10788740 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 991151 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 10.885062 # Average number of references to valid blocks.
+system.cpu.int_regfile_reads 551506175 # number of integer regfile reads
+system.cpu.int_regfile_writes 88407137 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8339 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2916 # number of floating regfile writes
+system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads
+system.cpu.misc_regfile_writes 912903 # number of misc regfile writes
+system.cpu.icache.replacements 990875 # number of replacements
+system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use
+system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.412932 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.996900 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.996900 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 10788740 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10788740 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10788740 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10788740 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10788740 # number of overall hits
-system.cpu.icache.overall_hits::total 10788740 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1074113 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1074113 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1074113 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1074113 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1074113 # number of overall misses
-system.cpu.icache.overall_misses::total 1074113 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14116777488 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14116777488 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14116777488 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14116777488 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14116777488 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14116777488 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11862853 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11862853 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11862853 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11862853 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11862853 # number of overall (read+write) accesses
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+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13066.751813 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13066.751813 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35237.121669 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35237.121669 # average WriteReq miss latency
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+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13303.951144 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14894.736842 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14894.736842 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30852.534087 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30852.534087 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 29089 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 14501 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2531 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.493086 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 57.543651 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 609134 # number of writebacks
-system.cpu.dcache.writebacks::total 609134 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 342186 # number of ReadReq MSHR hits
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-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1353 # number of LoadLockedReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 3054717 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total 3054717 # number of overall MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 387244 # number of ReadReq MSHR misses
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-system.cpu.dcache.WriteReq_mshr_misses::total 249083 # number of WriteReq MSHR misses
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-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12222 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 636327 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781960500 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152753421 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142066000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142066000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12934713921 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12934713921 # number of demand (read+write) MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 12934713921 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182355760000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28006419847 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28006419847 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210362179847 # number of overall MSHR uncacheable cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026452 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024299 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041044 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041044 # mshr miss rate for LoadLockedReq accesses
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-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025566 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025566 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025566 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025566 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.701336 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.701336 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32731.071253 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32731.071253 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11623.793160 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11623.793160 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20327.149282 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20327.149282 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20327.149282 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20327.149282 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 609133 # number of writebacks
+system.cpu.dcache.writebacks::total 609133 # number of writebacks
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1365 # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356641500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025567 # mshr miss rate for demand accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.612090 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.612090 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32704.911855 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32704.911855 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11571.977752 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11571.977752 # average LoadLockedReq mshr miss latency
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+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 64431 # number of replacements
-system.cpu.l2cache.tagsinuse 51361.955976 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1930789 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 129828 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 14.871900 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2488483415000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 36883.493474 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 44.395032 # Average occupied blocks per requestor
+system.cpu.l2cache.replacements 64428 # number of replacements
+system.cpu.l2cache.tagsinuse 51367.264734 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1930539 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 129823 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 14.870547 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2488482557500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 36879.772922 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 44.022997 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000230 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 8188.688040 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6245.379200 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.562797 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000677 # Average percentage of cache occupancy
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+system.cpu.l2cache.occ_blocks::cpu.data 6251.006645 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.124949 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.095297 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.783721 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 83246 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12089 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 977515 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 388648 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1461498 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 609134 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 609134 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 46 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112994 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112994 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 83246 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 12089 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 977515 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 501642 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1574492 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 83246 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 12089 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 977515 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 501642 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1574492 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 56 # number of ReadReq misses
+system.cpu.l2cache.occ_percent::cpu.inst 0.125007 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.095383 # Average percentage of cache occupancy
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166682463030 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18112015818 # number of WriteReq MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026724 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for demand accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::total 0.090296 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222853 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.090296 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40979.476225 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42280.789844 # average ReadReq mshr miss latency
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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.448382 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37908.793347 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1068189786972 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1068189786972 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88028 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 5.128875 # Number of seconds simulated
-sim_ticks 5128875494000 # Number of ticks simulated
-final_tick 5128875494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.132866 # Number of seconds simulated
+sim_ticks 5132866386000 # Number of ticks simulated
+final_tick 5132866386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 179743 # Simulator instruction rate (inst/s)
-host_op_rate 355302 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2259848354 # Simulator tick rate (ticks/s)
-host_mem_usage 404644 # Number of bytes of host memory used
-host_seconds 2269.57 # Real time elapsed on the host
-sim_insts 407937807 # Number of instructions simulated
-sim_ops 806381430 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2484160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1082048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10897856 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14467456 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1082048 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1082048 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9613376 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9613376 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38815 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16907 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 170279 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 226054 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 150209 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 150209 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 484348 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 574 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 210972 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2124804 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2820785 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 210972 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 210972 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1874363 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1874363 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1874363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 484348 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 574 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 210972 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2124804 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4695148 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 226054 # Total number of read requests seen
-system.physmem.writeReqs 150209 # Total number of write requests seen
-system.physmem.cpureqs 390083 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14467456 # Total number of bytes read from memory
-system.physmem.bytesWritten 9613376 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14467456 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9613376 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 85 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3870 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 13592 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 14674 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 12790 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 14969 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13832 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 14849 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 12900 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 14193 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 13720 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::12 13783 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 14903 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 12863 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15009 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 8622 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 8230 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 10302 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8995 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 10163 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8186 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 9599 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8962 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 10025 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 9289 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 10268 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8898 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 10138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 8164 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 10156 # Track writes on a per bank basis
+host_inst_rate 195837 # Simulator instruction rate (inst/s)
+host_op_rate 387119 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2464119438 # Simulator tick rate (ticks/s)
+host_mem_usage 403620 # Number of bytes of host memory used
+host_seconds 2083.04 # Real time elapsed on the host
+sim_insts 407937545 # Number of instructions simulated
+sim_ops 806384911 # Number of ops (including micro ops) simulated
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+system.physmem.bytes_inst_read::total 1081536 # Number of instructions bytes read from this memory
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+system.physmem.bw_read::pc.south_bridge.ide 482138 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu.data 2120397 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2813966 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 210708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 210708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1869789 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1869789 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1869789 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 4683755 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 225683 # Total number of read requests seen
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+system.physmem.bytesRead 14443712 # Total number of bytes read from memory
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+system.physmem.bytesConsumedWr 9597376 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 89 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 3846 # Reqs where no action is needed
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5128875413000 # Total gap between requests
+system.physmem.totGap 5132866305000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 226054 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 150209 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3329517724 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 7605839724 # Sum of mem lat for all requests
-system.physmem.totBusLat 903876000 # Total cycles spent in databus access
-system.physmem.totBankLat 3372446000 # Total cycles spent in bank access
-system.physmem.avgQLat 14734.40 # Average queueing delay per request
-system.physmem.avgBankLat 14924.37 # Average bank access latency per request
+system.physmem.totQLat 3339090244 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7604182244 # Sum of mem lat for all requests
+system.physmem.totBusLat 902376000 # Total cycles spent in databus access
+system.physmem.totBankLat 3362716000 # Total cycles spent in bank access
+system.physmem.avgQLat 14801.33 # Average queueing delay per request
+system.physmem.avgBankLat 14906.05 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 33658.77 # Average memory access latency
-system.physmem.avgRdBW 2.82 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 33707.38 # Average memory access latency
+system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.82 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 14.06 # Average write queue length over time
-system.physmem.readRowHits 199198 # Number of row buffer hits during reads
-system.physmem.writeRowHits 88428 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 58.87 # Row buffer hit rate for writes
-system.physmem.avgGap 13631091.58 # Average gap between requests
-system.iocache.replacements 47576 # number of replacements
-system.iocache.tagsinuse 0.091613 # Cycle average of tags in use
+system.physmem.avgWrQLen 10.11 # Average write queue length over time
+system.physmem.readRowHits 199074 # Number of row buffer hits during reads
+system.physmem.writeRowHits 88511 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 88.24 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 59.02 # Row buffer hit rate for writes
+system.physmem.avgGap 13664250.28 # Average gap between requests
+system.iocache.replacements 47575 # number of replacements
+system.iocache.tagsinuse 0.103977 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47591 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4991895066000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.091613 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.005726 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.005726 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
+system.iocache.warmup_cycle 4991894063000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.103977 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.006499 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
-system.iocache.overall_misses::total 47631 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143697932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 143697932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8983849160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 8983849160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 9127547092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 9127547092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 9127547092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 9127547092 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47630 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses
+system.iocache.overall_misses::total 47630 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143902932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 143902932 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9034164160 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 9034164160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 9178067092 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 9178067092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 9178067092 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 9178067092 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157736.478595 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 157736.478595 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192291.291952 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 192291.291952 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 191630.389704 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 191630.389704 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 56345 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158135.090110 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 158135.090110 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 193368.239726 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 193368.239726 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 192695.089062 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 192695.089062 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 60674 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 7566 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 7530 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 7.447132 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.057636 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96295990 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 96295990 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6552154765 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 6552154765 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 6648450755 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 6648450755 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96552990 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 96552990 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6602427338 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 6602427338 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 6698980328 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 6698980328 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105703.611416 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 105703.611416 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140243.038634 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 140243.038634 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106102.186813 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 106102.186813 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 141319.078296 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 141319.078296 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 448887765 # number of cpu cycles simulated
+system.cpu.numCycles 448858777 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 86493598 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 86493598 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1184200 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 81985656 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 79438611 # Number of BTB hits
+system.cpu.BPredUnit.lookups 86511552 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 86511552 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1187540 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 81908216 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 79448034 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 28044653 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 427268280 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86493598 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79438611 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 164008180 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5056188 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 124973 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 62751260 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 36198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 62335 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9257771 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 519239 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3803 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 258861392 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.258152 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.417945 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28014488 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 427358956 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86511552 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79448034 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 164036376 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5076610 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 125788 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 62760738 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 36372 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 61645 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9269515 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 518863 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3783 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 258886753 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.258580 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.418024 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 95283812 36.81% 36.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1591927 0.61% 37.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71954404 27.80% 65.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 971846 0.38% 65.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1615863 0.62% 66.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2450126 0.95% 67.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1121647 0.43% 67.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1424659 0.55% 68.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82447108 31.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 95280988 36.80% 36.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1593075 0.62% 37.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71954141 27.79% 65.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 971709 0.38% 65.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1620643 0.63% 66.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2451488 0.95% 67.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1122205 0.43% 67.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1426657 0.55% 68.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82465847 31.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 258861392 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192684 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.951838 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31762033 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60235448 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159762632 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3267698 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3833581 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 840104917 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 1244 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3833581 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34530134 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37412206 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10702091 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159938633 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12444747 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 836257763 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 19698 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5896480 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4716940 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 7816 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 997992319 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1816026440 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1816025416 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1024 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964353103 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 33639209 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 466352 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 473282 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28808345 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17312855 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10260076 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1206444 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 946818 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829834961 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1255797 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824342965 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 165215 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23689940 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36113140 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 203193 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 258861392 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.184496 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.385380 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 258886753 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192737 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.952101 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31742461 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60237035 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159788942 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3267328 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3850987 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 840289565 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1231 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3850987 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34512001 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37373607 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 10738522 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159961860 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12449776 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 836423195 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19229 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5893988 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4723761 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 7727 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 998196840 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1816454110 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1816453462 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964349930 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 33846903 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 467065 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 474165 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28825004 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17330743 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10271430 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1207742 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 944493 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 829965735 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1256270 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 824405499 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167750 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 23821216 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 36350655 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 203504 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 258886753 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.184425 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.385403 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 72001826 27.81% 27.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15596239 6.02% 33.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10365970 4.00% 37.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7555139 2.92% 40.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75952295 29.34% 70.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3901347 1.51% 71.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72539766 28.02% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 795622 0.31% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 153188 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 72013044 27.82% 27.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15598777 6.03% 33.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10365143 4.00% 37.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7553925 2.92% 40.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75959659 29.34% 70.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3903196 1.51% 71.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72545029 28.02% 99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 793969 0.31% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 154011 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 258861392 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 258886753 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 354431 33.41% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 554175 52.24% 85.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 152275 14.35% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 353413 33.31% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 554407 52.25% 85.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 153287 14.45% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 306719 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 796534260 96.63% 96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 307308 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 796584719 96.63% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18029662 2.19% 98.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9472324 1.15% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18039231 2.19% 98.85% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9474241 1.15% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824342965 # Type of FU issued
-system.cpu.iq.rate 1.836412 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1060881 # FU busy when requested
+system.cpu.iq.FU_type_0::total 824405499 # Type of FU issued
+system.cpu.iq.rate 1.836670 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1061107 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1908906757 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854790380 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819662460 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 825097030 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1650086 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_inst_queue_reads 1909060731 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 855053110 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 819712115 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 306 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 825159176 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1650601 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3338406 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 26898 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11294 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1845192 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3355072 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 26592 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11367 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1855422 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932288 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11793 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932171 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 11828 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3833581 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26182715 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2118325 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 831090758 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 325842 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17312855 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10260082 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 724912 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1616921 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11294 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 708686 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 624381 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1333067 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822327193 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17600649 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2015771 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3850987 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26145840 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2117101 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 831222005 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 328364 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17330743 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10271430 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 725551 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1616789 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 12654 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11367 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 710665 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 625080 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1335745 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 822377334 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17606524 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2028164 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26823265 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83275848 # Number of branches executed
-system.cpu.iew.exec_stores 9222616 # Number of stores executed
-system.cpu.iew.exec_rate 1.831922 # Inst execution rate
-system.cpu.iew.wb_sent 821819072 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819662518 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 640525310 # num instructions producing a value
-system.cpu.iew.wb_consumers 1046521436 # num instructions consuming a value
+system.cpu.iew.exec_refs 26829889 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83279279 # Number of branches executed
+system.cpu.iew.exec_stores 9223365 # Number of stores executed
+system.cpu.iew.exec_rate 1.832152 # Inst execution rate
+system.cpu.iew.wb_sent 821869918 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 819712181 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 640562059 # num instructions producing a value
+system.cpu.iew.wb_consumers 1046574799 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.825985 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.612052 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.826214 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.612056 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24603279 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052602 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1189396 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 255043204 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.161744 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.853415 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24730610 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1052764 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1192382 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 255051171 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.161659 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.853306 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 83146159 32.60% 32.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11856679 4.65% 37.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3955758 1.55% 38.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74970525 29.40% 68.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2479858 0.97% 69.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1486016 0.58% 69.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 951787 0.37% 70.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70929950 27.81% 97.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5266472 2.06% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 83143291 32.60% 32.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11860450 4.65% 37.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3961812 1.55% 38.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74971665 29.39% 68.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2481439 0.97% 69.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1489878 0.58% 69.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 950647 0.37% 70.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70929098 27.81% 97.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5262891 2.06% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11072 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total 11072 # number of overall misses
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+system.cpu.itb_walker_cache.demand_miss_latency::total 125220500 # number of demand (read+write) miss cycles
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+system.cpu.itb_walker_cache.overall_miss_latency::total 125220500 # number of overall miss cycles
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system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
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-system.cpu.itb_walker_cache.demand_accesses::total 40545 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40545 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 40545 # number of overall (read+write) accesses
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-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275344 # miss rate for ReadReq accesses
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-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11032.876467 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11032.876467 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11032.876467 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11032.876467 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40794 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 40794 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40794 # number of overall (read+write) accesses
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+system.cpu.itb_walker_cache.demand_miss_rate::total 0.271412 # miss rate for demand accesses
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+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11309.654986 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11309.654986 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 1731 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 1731 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11163 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11163 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11163 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 11163 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11163 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 11163 # number of overall MSHR misses
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-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 100834000 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 100834000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 100834000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 100834000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275344 # mshr miss rate for ReadReq accesses
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-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275324 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275324 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9032.876467 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks 1966 # number of writebacks
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+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for demand accesses
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+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for overall accesses
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+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9309.654986 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency
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+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 109401 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 13.751867 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 137796 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 109417 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.259366 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5100515626500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.751867 # Average occupied blocks per requestor
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-system.cpu.dtb_walker_cache.occ_percent::total 0.859492 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137796 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 137796 # number of ReadReq hits
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-system.cpu.dtb_walker_cache.overall_hits::total 137796 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110443 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 110443 # number of ReadReq misses
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-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1382584000 # number of overall miss cycles
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-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248239 # number of ReadReq accesses(hits+misses)
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-system.cpu.dtb_walker_cache.demand_accesses::total 248239 # number of demand (read+write) accesses
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-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.444906 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.444906 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.444906 # miss rate for overall accesses
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-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12518.529920 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12518.529920 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12518.529920 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12518.529920 # average overall miss latency
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+system.cpu.dtb_walker_cache.total_refs 137445 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs 112536 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs 1.221343 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5100518873000 # Cycle when the warmup percentage was hit.
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+system.cpu.dtb_walker_cache.occ_percent::total 0.809849 # Average percentage of cache occupancy
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+system.cpu.dtb_walker_cache.ReadReq_hits::total 137452 # number of ReadReq hits
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+system.cpu.dtb_walker_cache.demand_hits::total 137452 # number of demand (read+write) hits
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+system.cpu.dtb_walker_cache.ReadReq_misses::total 113500 # number of ReadReq misses
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+system.cpu.dtb_walker_cache.demand_misses::total 113500 # number of demand (read+write) misses
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+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1432388500 # number of demand (read+write) miss cycles
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+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1432388500 # number of overall miss cycles
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+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 250952 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 250952 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 250952 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 250952 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 250952 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 250952 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452278 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452278 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452278 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452278 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452278 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452278 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12620.162996 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12620.162996 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12620.162996 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12620.162996 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 36585 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 36585 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110443 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110443 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110443 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 110443 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110443 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 110443 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of ReadReq MSHR miss cycles
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-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1161698000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1161698000 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.444906 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.444906 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.444906 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10518.529920 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency
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-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency
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+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.replacements 1671903 # number of replacements
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system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 1.950813 # Number of seconds simulated
-sim_ticks 1950813247500 # Number of ticks simulated
-final_tick 1950813247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.950814 # Number of seconds simulated
+sim_ticks 1950813955500 # Number of ticks simulated
+final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1287440 # Simulator instruction rate (inst/s)
-host_op_rate 1287440 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41184614921 # Simulator tick rate (ticks/s)
+host_inst_rate 770652 # Simulator instruction rate (inst/s)
+host_op_rate 770652 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24652738853 # Simulator tick rate (ticks/s)
host_mem_usage 325660 # Number of bytes of host memory used
-host_seconds 47.37 # Real time elapsed on the host
-sim_insts 60982794 # Number of instructions simulated
-sim_ops 60982794 # Number of ops (including micro ops) simulated
+host_seconds 79.13 # Real time elapsed on the host
+sim_insts 60983017 # Number of instructions simulated
+sim_ops 60983017 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24727680 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 439808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28684096 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7706368 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7706368 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 386370 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6872 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 448189 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 120412 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 120412 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12675575 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1358859 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 225449 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14703661 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3950336 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3950336 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3950336 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12675575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1358859 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 225449 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18653997 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 448189 # Total number of read requests seen
-system.physmem.writeReqs 120412 # Total number of write requests seen
-system.physmem.cpureqs 599134 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28684096 # Total number of bytes read from memory
-system.physmem.bytesWritten 7706368 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28684096 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7706368 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 448191 # Total number of read requests seen
+system.physmem.writeReqs 120414 # Total number of write requests seen
+system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28684224 # Total number of bytes read from memory
+system.physmem.bytesWritten 7706496 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 7172 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27647 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 522 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1950759532000 # Total gap between requests
+system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1950760240000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 448189 # Categorize read packet sizes
+system.physmem.readPktSize::6 448191 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 120934 # categorize write packet sizes
+system.physmem.writePktSize::6 120944 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 7172 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 409832 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 7493 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5295 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2367 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::5 2388 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1774 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4346 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::2 5068 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 41 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2865774804 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 10947900804 # Sum of mem lat for all requests
-system.physmem.totBusLat 1792528000 # Total cycles spent in databus access
-system.physmem.totBankLat 6289598000 # Total cycles spent in bank access
-system.physmem.avgQLat 6394.93 # Average queueing delay per request
-system.physmem.avgBankLat 14035.15 # Average bank access latency per request
+system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests
+system.physmem.totBusLat 1792536000 # Total cycles spent in databus access
+system.physmem.totBankLat 6288996000 # Total cycles spent in bank access
+system.physmem.avgQLat 6509.40 # Average queueing delay per request
+system.physmem.avgBankLat 14033.74 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24430.08 # Average memory access latency
+system.physmem.avgMemAccLat 24543.14 # Average memory access latency
system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 10.50 # Average write queue length over time
-system.physmem.readRowHits 428033 # Number of row buffer hits during reads
-system.physmem.writeRowHits 76777 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads
+system.physmem.avgWrQLen 10.51 # Average write queue length over time
+system.physmem.readRowHits 428061 # Number of row buffer hits during reads
+system.physmem.writeRowHits 76773 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes
-system.physmem.avgGap 3430805.67 # Average gap between requests
-system.l2c.replacements 341333 # number of replacements
-system.l2c.tagsinuse 65247.038846 # Cycle average of tags in use
-system.l2c.total_refs 2438074 # Total number of references to valid blocks.
-system.l2c.sampled_refs 406309 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.000541 # Average number of references to valid blocks.
+system.physmem.avgGap 3430782.78 # Average gap between requests
+system.l2c.replacements 341335 # number of replacements
+system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use
+system.l2c.total_refs 2438054 # Total number of references to valid blocks.
+system.l2c.sampled_refs 406311 # Sample count of references to valid blocks.
+system.l2c.avg_refs 6.000463 # Average number of references to valid blocks.
system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 55545.297156 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4807.218464 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 4686.690338 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 164.376104 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 43.456784 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.847554 # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 674220 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 658221 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 328583 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 113537 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1774561 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 791464 # number of Writeback hits
-system.l2c.Writeback_hits::total 791464 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits
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+system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu1.data 113535 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1774538 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 791470 # number of Writeback hits
+system.l2c.Writeback_hits::total 791470 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 738 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 123896 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 48958 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 172854 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 674220 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 782117 # number of demand (read+write) hits
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system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 227555.877118 # average WriteReq miss latency
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-system.iocache.demand_avg_miss_latency::total 227105.799559 # average overall miss latency
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-system.iocache.overall_avg_miss_latency::total 227105.799559 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 186741 # number of cycles access was blocked
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+system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked
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-system.iocache.blocked::no_mshrs 23044 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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+system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles
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system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency
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-system.iocache.WriteReq_avg_mshr_miss_latency::total 175506.089286 # average WriteReq mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 7424678 # DTB read hits
+system.cpu0.dtb.read_hits 7424685 # DTB read hits
system.cpu0.dtb.read_misses 7443 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
system.cpu0.dtb.read_accesses 490673 # DTB read accesses
-system.cpu0.dtb.write_hits 5011102 # DTB write hits
+system.cpu0.dtb.write_hits 5011105 # DTB write hits
system.cpu0.dtb.write_misses 813 # DTB write misses
system.cpu0.dtb.write_acv 134 # DTB write access violations
system.cpu0.dtb.write_accesses 187452 # DTB write accesses
-system.cpu0.dtb.data_hits 12435780 # DTB hits
+system.cpu0.dtb.data_hits 12435790 # DTB hits
system.cpu0.dtb.data_misses 8256 # DTB misses
system.cpu0.dtb.data_acv 344 # DTB access violations
system.cpu0.dtb.data_accesses 678125 # DTB accesses
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3900399022 # number of cpu cycles simulated
+system.cpu0.numCycles 3900399041 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 47350752 # Number of instructions committed
-system.cpu0.committedOps 47350752 # Number of ops (including micro ops) committed
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+system.cpu0.committedInsts 47350784 # Number of instructions committed
+system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed
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system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses
system.cpu0.num_func_calls 1188579 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 5567605 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 43919757 # number of integer instructions
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system.cpu0.num_fp_insts 206365 # number of float instructions
-system.cpu0.num_int_register_reads 60378447 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 32741783 # number of times the integer registers were written
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+system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written
-system.cpu0.num_mem_refs 12475681 # number of memory refs
-system.cpu0.num_load_insts 7451619 # Number of load instructions
-system.cpu0.num_store_insts 5024062 # Number of store instructions
-system.cpu0.num_idle_cycles 3698907701.219057 # Number of idle cycles
-system.cpu0.num_busy_cycles 201491320.780943 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.051659 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.948341 # Percentage of idle cycles
+system.cpu0.num_mem_refs 12475691 # number of memory refs
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+system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed
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system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1898626830000 97.36% 97.36% # number of cycles we spent at this ipl
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-system.cpu0.kern.ipl_ticks::22 759970000 0.04% 97.40% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 326793000 0.02% 97.42% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 50392837500 2.58% 100.00% # number of cycles we spent at this ipl
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+system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl
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+system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1946498286500 99.83% 99.83% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3025 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 686559 # number of replacements
-system.cpu0.icache.tagsinuse 509.179293 # Cycle average of tags in use
-system.cpu0.icache.total_refs 46672188 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 687071 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 67.929207 # Average number of references to valid blocks.
+system.cpu0.icache.replacements 686544 # number of replacements
+system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use
+system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.179293 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 46672188 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 46672188 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014510 # miss rate for ReadReq accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 13938.126124 # average ReadReq miss latency
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 8203450500 # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.demand_mshr_miss_latency::total 8203450500 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.icache.overall_mshr_miss_latency::total 8203450500 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014510 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for demand accesses
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11938.126124 # average ReadReq mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1171741 # number of replacements
-system.cpu0.dcache.tagsinuse 505.264481 # Cycle average of tags in use
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system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy
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system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051328 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051328 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088494 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088494 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.097377 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.097377 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20315.102246 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20315.102246 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29136.087933 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29136.087933 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8754.874963 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8754.874963 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5581.050427 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5581.050427 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2500235 # DTB read hits
+system.cpu1.dtb.read_hits 2500361 # DTB read hits
system.cpu1.dtb.read_misses 2992 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
-system.cpu1.dtb.write_hits 1820988 # DTB write hits
+system.cpu1.dtb.write_hits 1820984 # DTB write hits
system.cpu1.dtb.write_misses 341 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
-system.cpu1.dtb.data_hits 4321223 # DTB hits
+system.cpu1.dtb.data_hits 4321345 # DTB hits
system.cpu1.dtb.data_misses 3333 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344610 # DTB accesses
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3901626495 # number of cpu cycles simulated
+system.cpu1.numCycles 3901627911 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 13632042 # Number of instructions committed
-system.cpu1.committedOps 13632042 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 12571491 # Number of integer alu accesses
+system.cpu1.committedInsts 13632233 # Number of instructions committed
+system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses
-system.cpu1.num_func_calls 426717 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1355011 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 12571491 # number of integer instructions
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+system.cpu1.num_int_insts 12571690 # number of integer instructions
system.cpu1.num_fp_insts 180459 # number of float instructions
-system.cpu1.num_int_register_reads 17311598 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 9221787 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written
-system.cpu1.num_mem_refs 4345531 # number of memory refs
-system.cpu1.num_load_insts 2514982 # Number of load instructions
-system.cpu1.num_store_insts 1830549 # Number of store instructions
-system.cpu1.num_idle_cycles 3850258507.998026 # Number of idle cycles
-system.cpu1.num_busy_cycles 51367987.001974 # Number of busy cycles
+system.cpu1.num_mem_refs 4345653 # number of memory refs
+system.cpu1.num_load_insts 2515108 # Number of load instructions
+system.cpu1.num_store_insts 1830545 # Number of store instructions
+system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles
+system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles
system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1907138262500 97.76% 97.76% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 705201000 0.04% 97.80% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 364168000 0.02% 97.82% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 42604858000 2.18% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1950812489500 # number of cycles we spent at this ipl
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+system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 73828 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 2126 # number of protection mode switches
+system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches
system.cpu1.kern.mode_switch::user 465 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2924 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 915
system.cpu1.kern.mode_good::user 465
system.cpu1.kern.mode_good::idle 450
-system.cpu1.kern.mode_switch_good::kernel 0.430386 # fraction of useful protection mode switches
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system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.153899 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 18665784500 0.96% 0.96% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1711228500 0.09% 1.04% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1930435473000 98.96% 100.00% # number of ticks spent at the given mode
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system.cpu1.kern.swap_context 2086 # number of times the context was actually changed
-system.cpu1.icache.replacements 328648 # number of replacements
-system.cpu1.icache.tagsinuse 446.257828 # Cycle average of tags in use
-system.cpu1.icache.total_refs 13306209 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 329160 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 40.424745 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1948917036000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 446.257828 # Average occupied blocks per requestor
+system.cpu1.icache.replacements 328646 # number of replacements
+system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use
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+system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 13306209 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 13306209 # number of ReadReq hits
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-system.cpu1.icache.overall_misses::total 329196 # number of overall misses
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 13205.976075 # average ReadReq miss latency
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+system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329196 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 329196 # number of ReadReq MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 329196 # number of overall MSHR misses
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system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits
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+system.cpu1.dcache.demand_avg_miss_latency::total 14153.568959 # average overall miss latency
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723171500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723171500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742552500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742552500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050253 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050253 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036709 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156916 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156916 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103995 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103995 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.044586 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.044586 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10120.581648 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10120.581648 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.234827 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.234827 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.551514 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.551514 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5246.540778 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5246.540778 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
sim_ticks 1910582068000 # Number of ticks simulated
final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1092208 # Simulator instruction rate (inst/s)
-host_op_rate 1092208 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 37180157619 # Simulator tick rate (ticks/s)
-host_mem_usage 321564 # Number of bytes of host memory used
-host_seconds 51.39 # Real time elapsed on the host
+host_inst_rate 942466 # Simulator instruction rate (inst/s)
+host_op_rate 942466 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32082735017 # Simulator tick rate (ticks/s)
+host_mem_usage 321492 # Number of bytes of host memory used
+host_seconds 59.55 # Real time elapsed on the host
sim_insts 56125446 # Number of instructions simulated
sim_ops 56125446 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1891670000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1891670000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223220000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223220000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229367500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229367500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses
---------- Begin Simulation Statistics ----------
sim_seconds 1.182883 # Number of seconds simulated
-sim_ticks 1182883077500 # Number of ticks simulated
-final_tick 1182883077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1182883275000 # Number of ticks simulated
+final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 330156 # Simulator instruction rate (inst/s)
-host_op_rate 420694 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6355289452 # Simulator tick rate (ticks/s)
-host_mem_usage 400808 # Number of bytes of host memory used
-host_seconds 186.13 # Real time elapsed on the host
-sim_insts 61450599 # Number of instructions simulated
-sim_ops 78301940 # Number of ops (including micro ops) simulated
+host_inst_rate 656929 # Simulator instruction rate (inst/s)
+host_op_rate 837075 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 12645375755 # Simulator tick rate (ticks/s)
+host_mem_usage 400812 # Number of bytes of host memory used
+host_seconds 93.54 # Real time elapsed on the host
+sim_insts 61450949 # Number of instructions simulated
+sim_ops 78302298 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4712308 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4776304 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62110116 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4085952 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7113296 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 73702 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 74656 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6653925 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 63843 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 820679 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43879664 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3983748 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4037850 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52507401 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3454232 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6013524 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3454232 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43879664 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3998120 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6582771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58520925 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6653925 # Total number of read requests seen
-system.physmem.writeReqs 820679 # Total number of write requests seen
-system.physmem.cpureqs 271820 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 425851200 # Total number of bytes read from memory
-system.physmem.bytesWritten 52523456 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62110116 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7113296 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6653924 # Total number of read requests seen
+system.physmem.writeReqs 820678 # Total number of write requests seen
+system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 425851136 # Total number of bytes read from memory
+system.physmem.bytesWritten 52523392 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 11750 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 415465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50651 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1182878628500 # Total gap between requests
+system.physmem.totGap 1182878800500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159036 # Categorize read packet sizes
+system.physmem.readPktSize::6 159035 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 63843 # categorize write packet sizes
+system.physmem.writePktSize::6 63842 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 11750 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 6597380 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 40502 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 11414 # What read queue length does an incoming req see
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system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
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-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059319 # miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047690 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13738.038886 # average ReadReq miss latency
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-system.cpu0.dcache.WriteReq_avg_miss_latency::total 29156.888484 # average WriteReq miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9466.395112 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5936.099253 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5936.099253 # average StoreCondReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 19645.160593 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19645.160593 # average overall miss latency
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+system.cpu0.dcache.occ_percent::cpu0.data 0.886397 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.886397 # Average percentage of cache occupancy
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+system.cpu0.dcache.ReadReq_hits::total 6602660 # number of ReadReq hits
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+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13745.938464 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29122.595306 # average WriteReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 19640.712545 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 19640.712545 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 306622 # number of writebacks
-system.cpu0.dcache.writebacks::total 306622 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228156 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 228156 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141693 # number of WriteReq MSHR misses
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9329 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7493 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 369849 # number of overall MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678104000 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3847941000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69654000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69654000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29513000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::total 6526045000 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total 6526045000 # number of overall MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559793500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033402 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025786 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059319 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059319 # mshr miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11738.038886 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11738.038886 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27156.888484 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27156.888484 # average WriteReq mshr miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7466.395112 # average LoadLockedReq mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3938.742827 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 306514 # number of writebacks
+system.cpu0.dcache.writebacks::total 306514 # number of writebacks
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9328 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69630000 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13560077000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.938464 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.938464 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27122.595306 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27122.595306 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7464.622642 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7464.622642 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3931.432768 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 8308478 # DTB read hits
-system.cpu1.dtb.read_misses 3644 # DTB read misses
-system.cpu1.dtb.write_hits 5825596 # DTB write hits
-system.cpu1.dtb.write_misses 1434 # DTB write misses
+system.cpu1.dtb.read_hits 8308581 # DTB read hits
+system.cpu1.dtb.read_misses 3643 # DTB read misses
+system.cpu1.dtb.write_hits 5825594 # DTB write hits
+system.cpu1.dtb.write_misses 1436 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 8312122 # DTB read accesses
+system.cpu1.dtb.read_accesses 8312224 # DTB read accesses
system.cpu1.dtb.write_accesses 5827030 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 14134074 # DTB hits
-system.cpu1.dtb.misses 5078 # DTB misses
-system.cpu1.dtb.accesses 14139152 # DTB accesses
-system.cpu1.itb.inst_hits 33188345 # ITB inst hits
+system.cpu1.dtb.hits 14134175 # DTB hits
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+system.cpu1.dtb.accesses 14139254 # DTB accesses
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system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 33190516 # ITB inst accesses
-system.cpu1.itb.hits 33188345 # DTB hits
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system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 33190516 # DTB accesses
-system.cpu1.numCycles 2364324255 # number of cpu cycles simulated
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32577871 # Number of instructions committed
-system.cpu1.committedOps 41082259 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 37307050 # Number of integer alu accesses
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system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
system.cpu1.num_func_calls 961975 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3732476 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 37307050 # number of integer instructions
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system.cpu1.num_fp_insts 6793 # number of float instructions
-system.cpu1.num_int_register_reads 213626787 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 39450306 # number of times the integer registers were written
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system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
-system.cpu1.num_mem_refs 14671800 # number of memory refs
-system.cpu1.num_load_insts 8630367 # Number of load instructions
-system.cpu1.num_store_insts 6041433 # Number of store instructions
-system.cpu1.num_idle_cycles 1868325738.966939 # Number of idle cycles
-system.cpu1.num_busy_cycles 495998516.033061 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.209784 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.790216 # Percentage of idle cycles
+system.cpu1.num_mem_refs 14671912 # number of memory refs
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+system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 43884 # number of quiesce instructions executed
-system.cpu1.icache.replacements 469230 # number of replacements
-system.cpu1.icache.tagsinuse 478.783120 # Cycle average of tags in use
-system.cpu1.icache.total_refs 32718599 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 469742 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 69.652275 # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed
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system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 478.783120 # Average occupied blocks per requestor
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system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy
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-system.cpu1.icache.demand_hits::total 32718599 # number of demand (read+write) hits
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-system.cpu1.icache.overall_hits::total 32718599 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 469742 # number of ReadReq misses
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-system.cpu1.icache.overall_misses::total 469742 # number of overall misses
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-system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188341 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13514.895411 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13514.895411 # average ReadReq miss latency
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-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5409030000 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.demand_mshr_miss_latency::total 5409030000 # number of demand (read+write) MSHR miss cycles
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system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles
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-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency
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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.dcache.warmup_cycle 83625331000 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.ReadReq_hits::total 6944275 # number of ReadReq hits
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-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81753 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 81753 # number of LoadLockedReq hits
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-system.cpu1.dcache.StoreCondReq_hits::total 82700 # number of StoreCondReq hits
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-system.cpu1.dcache.overall_hits::total 11769818 # number of overall hits
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-system.cpu1.dcache.LoadLockedReq_misses::total 11060 # number of LoadLockedReq misses
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-system.cpu1.dcache.StoreCondReq_misses::total 10038 # number of StoreCondReq misses
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-system.cpu1.dcache.overall_misses::total 320038 # number of overall misses
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
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system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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sim_ticks 2603636076000 # Number of ticks simulated
final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes
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projects / gem5.git / commitdiff