New variables.
(struct elf32_arm_link_hash_table): New member `nacl_p'.
(elf32_arm_link_hash_table_create): Initialize it.
(elf32_arm_nacl_link_hash_table_create): New function.
(arm_movw_immediate, arm_movt_immediate): New functions.
(elf32_arm_populate_plt_entry): Test HTAB->nacl_p.
(elf32_arm_finish_dynamic_sections): Likewise.
(elf32_arm_output_plt_map_1): Likewise.
(bfd_elf32_littlearm_nacl_vec, bfd_elf32_bigarm_nacl_vec):
New backend vector stanza.
(elf32_arm_nacl_modify_segment_map): New function.
* config.bfd: Handle arm-*-nacl*, armeb-*-nacl*.
* targets.c: Support bfd_elf32_{big,little}_nacl_vec.
* configure.in: Likewise.
(bfd_elf32_bigarm_nacl_vec): Add elf-nacl.lo here.
(bfd_elf32_littlearm_nacl_vec): Likewise.
(bfd_elf32_bigarm_vec, bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerated.
* configure.tgt (arm-*-nacl*): Match it.
* config/te-nacl.h (FPU_DEFAULT, EABI_DEFAULT): Define.
(LOCAL_LABELS_DOLLAR): Define.
* config/tc-arm.c (elf32_arm_target_format) [TE_NACL]:
Use nacl format variants.
* gas/elf/elf.exp (run_elf_list_test): Treat arm-*-nacl* targets
as -armeabi.
* gas/arm/any-idiv.d: Match *-*-nacl* targets too.
* gas/arm/arch4t.d: Likewise.
* gas/arm/arch4t-eabi.d: Likewise.
* gas/arm/attr-any-armv4t.d: Likewise.
* gas/arm/attr-any-thumbv6.d: Likewise.
* gas/arm/attr-cpu-directive.d: Likewise.
* gas/arm/attr-default.d: Likewise.
* gas/arm/attr-march-all.d: Likewise.
* gas/arm/attr-march-armv1.d: Likewise.
* gas/arm/attr-march-armv2a.d: Likewise.
* gas/arm/attr-march-armv2.d: Likewise.
* gas/arm/attr-march-armv2s.d: Likewise.
* gas/arm/attr-march-armv3.d: Likewise.
* gas/arm/attr-march-armv3m.d: Likewise.
* gas/arm/attr-march-armv4.d: Likewise.
* gas/arm/attr-march-armv4t.d: Likewise.
* gas/arm/attr-march-armv4txm.d: Likewise.
* gas/arm/attr-march-armv4xm.d: Likewise.
* gas/arm/attr-march-armv5.d: Likewise.
* gas/arm/attr-march-armv5t.d: Likewise.
* gas/arm/attr-march-armv5te.d: Likewise.
* gas/arm/attr-march-armv5tej.d: Likewise.
* gas/arm/attr-march-armv5texp.d: Likewise.
* gas/arm/attr-march-armv5txm.d: Likewise.
* gas/arm/attr-march-armv6.d: Likewise.
* gas/arm/attr-march-armv6j.d: Likewise.
* gas/arm/attr-march-armv6k.d: Likewise.
* gas/arm/attr-march-armv6k+sec.d: Likewise.
* gas/arm/attr-march-armv6kt2.d: Likewise.
* gas/arm/attr-march-armv6-m.d: Likewise.
* gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/arm/attr-march-armv6s-m.d: Likewise.
* gas/arm/attr-march-armv6t2.d: Likewise.
* gas/arm/attr-march-armv6z.d: Likewise.
* gas/arm/attr-march-armv6zk.d: Likewise.
* gas/arm/attr-march-armv6zkt2.d: Likewise.
* gas/arm/attr-march-armv6zt2.d: Likewise.
* gas/arm/attr-march-armv7-a.d: Likewise.
* gas/arm/attr-march-armv7a.d: Likewise.
* gas/arm/attr-march-armv7-a+idiv.d: Likewise.
* gas/arm/attr-march-armv7-a+mp.d: Likewise.
* gas/arm/attr-march-armv7-a+sec.d: Likewise.
* gas/arm/attr-march-armv7-a+sec+virt.d: Likewise.
* gas/arm/attr-march-armv7-a+virt.d: Likewise.
* gas/arm/attr-march-armv7.d: Likewise.
* gas/arm/attr-march-armv7em.d: Likewise.
* gas/arm/attr-march-armv7-m.d: Likewise.
* gas/arm/attr-march-armv7m.d: Likewise.
* gas/arm/attr-march-armv7-r.d: Likewise.
* gas/arm/attr-march-armv7r.d: Likewise.
* gas/arm/attr-march-armv7-r+mp.d: Likewise.
* gas/arm/attr-march-iwmmxt2.d: Likewise.
* gas/arm/attr-march-iwmmxt.d: Likewise.
* gas/arm/attr-march-xscale.d: Likewise.
* gas/arm/attr-mcpu.d: Likewise.
* gas/arm/attr-mfpu-arm1020e.d: Likewise.
* gas/arm/attr-mfpu-arm1020t.d: Likewise.
* gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
* gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
* gas/arm/attr-mfpu-arm7500fe.d: Likewise.
* gas/arm/attr-mfpu-fpa10.d: Likewise.
* gas/arm/attr-mfpu-fpa11.d: Likewise.
* gas/arm/attr-mfpu-fpa.d: Likewise.
* gas/arm/attr-mfpu-fpe2.d: Likewise.
* gas/arm/attr-mfpu-fpe3.d: Likewise.
* gas/arm/attr-mfpu-fpe.d: Likewise.
* gas/arm/attr-mfpu-maverick.d: Likewise.
* gas/arm/attr-mfpu-neon.d: Likewise.
* gas/arm/attr-mfpu-neon-fp16.d: Likewise.
* gas/arm/attr-mfpu-softfpa.d: Likewise.
* gas/arm/attr-mfpu-softvfp.d: Likewise.
* gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
* gas/arm/attr-mfpu-vfp10.d: Likewise.
* gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
* gas/arm/attr-mfpu-vfp3.d: Likewise.
* gas/arm/attr-mfpu-vfp9.d: Likewise.
* gas/arm/attr-mfpu-vfp.d: Likewise.
* gas/arm/attr-mfpu-vfpv2.d: Likewise.
* gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv3.d: Likewise.
* gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv4.d: Likewise.
* gas/arm/attr-mfpu-vfpxd.d: Likewise.
* gas/arm/attr-names.d: Likewise.
* gas/arm/attr-order.d: Likewise.
* gas/arm/attr-override-cpu-directive.d: Likewise.
* gas/arm/attr-override-mcpu.d: Likewise.
* gas/arm/got_prel.d: Likewise.
* gas/arm/mapdir.d: Likewise.
* gas/arm/mapmisc.d: Likewise.
* gas/arm/mapsecs.d: Likewise.
* gas/arm/mapshort-eabi.d: Likewise.
* gas/arm/mapshort-elf.d: Likewise.
* gas/arm/mov-highregs-any.d: Likewise.
* gas/arm/mov-lowregs-any.d: Likewise.
* gas/arm/pr12198-1.d: Likewise.
* gas/arm/pr12198-2.d: Likewise.
* gas/arm/thumb.d: Likewise.
* gas/arm/thumb-eabi.d: Likewise.
* gas/arm/thumbrel.d: Likewise.
* configure.tgt (arm*-*-nacl*, arm*b-*-nacl*): Handle them.
* emulparams/armelf_nacl.sh: New file.
* emulparams/armelfb_nacl.sh: New file.
* Makefile.am (ALL_EMULATION_SOURCES): Add earmelf_nacl.c
and earmelfb_nacl.c here.
(earmelf_nacl.c, earmelfb_nacl.c): New targets.
* Makefile.in: Regenerated.
* ld-arm/arm-elf.exp (armelftests): Split out into ...
(armelftests_common, armelftests_nonacl): ... these two.
(armeabitests): Split out into ...
(armeabitests_common, armeabitests_nonacl): ... these two.
Omit _nonacl sets for arm*-*-nacl* targets.
* ld-arm/farcall-mix.d: Don't match exact addresses, only symbolic ones.
* ld-arm/farcall-mix2.d: Likewise.
* ld-arm/farcall-group.d: Likewise.
* ld-arm/tls-gdesc-got.d: Match variant file formats too.
Accept some variation in exact addresses.
* ld-arm/thumb2-b-interwork.d: Match variant file formats too.
Fix regexps not to care about exact addresses where not relevant.
* ld-arm/thumb2-bl-undefweak.d: Match any hex strings, not any
strings of particular exact lengths.
* ld-arm/thumb2-bl-undefweak1.d: Likewise.
* ld-arm/arm-app.r: Match variant file formats too.
* ld-arm/arm-app-abs32.r: Likewise.
* ld-arm/arm-lib.d: Likewise.
* ld-arm/arm-lib.r: Likewise.
* ld-arm/arm-static-app.r: Likewise.
* ld-arm/armv4-bx.d: Likewise.
* ld-arm/data-only-map.d: Likewise.
* ld-arm/group-relocs.d: Likewise.
* ld-arm/jump19.d: Likewise.
* ld-arm/reloc-boundaries.d: Likewise.
* ld-arm/thumb1-bl.d: Likewise.
* ld-arm/thumb2-bl.d: Likewise.
* ld-arm/tls-app.d: Likewise.
* ld-arm/tls-app.r: Likewise.
* ld-arm/tls-gdierelax.d: Likewise.
* ld-arm/tls-gdierelax2.d: Likewise.
* ld-arm/tls-gdlerelax.d: Likewise.
* ld-arm/tls-lib.d: Likewise.
* ld-arm/tls-lib.r: Likewise.
* ld-arm/tls-mixed.r: Likewise.
* ld-arm/vfp11-fix-none.d: Likewise.
* ld-arm/vfp11-fix-scalar.d: Likewise.
* ld-arm/vfp11-fix-vector.d: Likewise.
* ld-arm/arm-static-app.d: Likewise.
Fix regexps not to care about exact number of leading spaces.
* ld-arm/arm-app-abs32.d: Likewise.
* ld-arm/fix-arm1176-off.d: Likewise.
* ld-arm/fix-arm1176-on.d: Likewise.
* ld-arm/arm-elf.exp: Treat nacl targets like eabi targets.
+2012-04-12 Roland McGrath <mcgrathr@google.com>
+
+ * elf32-arm.c (elf32_arm_nacl_plt0_entry, elf32_arm_nacl_plt_entry):
+ New variables.
+ (struct elf32_arm_link_hash_table): New member `nacl_p'.
+ (elf32_arm_link_hash_table_create): Initialize it.
+ (elf32_arm_nacl_link_hash_table_create): New function.
+ (arm_movw_immediate, arm_movt_immediate): New functions.
+ (elf32_arm_populate_plt_entry): Test HTAB->nacl_p.
+ (elf32_arm_finish_dynamic_sections): Likewise.
+ (elf32_arm_output_plt_map_1): Likewise.
+ (bfd_elf32_littlearm_nacl_vec, bfd_elf32_bigarm_nacl_vec):
+ New backend vector stanza.
+ (elf32_arm_nacl_modify_segment_map): New function.
+ * config.bfd: Handle arm-*-nacl*, armeb-*-nacl*.
+ * targets.c: Support bfd_elf32_{big,little}_nacl_vec.
+ * configure.in: Likewise.
+ (bfd_elf32_bigarm_nacl_vec): Add elf-nacl.lo here.
+ (bfd_elf32_littlearm_nacl_vec): Likewise.
+ (bfd_elf32_bigarm_vec, bfd_elf32_littlearm_vec): Likewise.
+ (bfd_elf32_bigarm_symbian_vec): Likewise.
+ (bfd_elf32_littlearm_symbian_vec): Likewise.
+ (bfd_elf32_bigarm_vxworks_vec): Likewise.
+ (bfd_elf32_littlearm_vxworks_vec): Likewise.
+ * configure: Regenerated.
+
2012-04-12 Tristan Gingold <gingold@adacore.com>
* elflink.c (elf_link_output_extsym): Add a guard.
targ_selvecs=bfd_elf32_bigarc_vec
;;
+ arm-*-nacl*)
+ targ_defvec=bfd_elf32_littlearm_nacl_vec
+ targ_selvecs="bfd_elf32_bigarm_nacl_vec bfd_elf32_i386_nacl_vec"
+ targ64_selvecs="bfd_elf32_x86_64_nacl_vec bfd_elf64_x86_64_nacl_vec"
+ targ_archs="$targ_archs bfd_i386_arch"
+ ;;
+ armeb-*-nacl*)
+ targ_defvec=bfd_elf32_bigarm_nacl_vec
+ targ_selvecs="bfd_elf32_littlearm_nacl_vec bfd_elf32_i386_nacl_vec"
+ targ64_selvecs="bfd_elf32_x86_64_nacl_vec bfd_elf64_x86_64_nacl_vec"
+ targ_archs="$targ_archs bfd_i386_arch"
+ ;;
armeb-*-netbsdelf*)
targ_defvec=bfd_elf32_bigarm_vec
targ_selvecs="bfd_elf32_littlearm_vec armnetbsd_vec"
;;
i[3-7]86-*-nacl*)
targ_defvec=bfd_elf32_i386_nacl_vec
- targ_selvecs="bfd_elf32_i386_vec"
+ targ_selvecs="bfd_elf32_bigarm_nacl_vec bfd_elf32_littlearm_nacl_vec"
targ64_selvecs="bfd_elf64_x86_64_nacl_vec bfd_elf32_x86_64_nacl_vec"
+ targ_archs="$targ_archs bfd_arm_arch"
;;
#ifdef BFD64
x86_64-*-darwin*)
;;
x86_64-*-nacl*)
targ_defvec=bfd_elf32_x86_64_nacl_vec
- targ_selvecs="bfd_elf32_i386_nacl_vec bfd_elf64_x86_64_nacl_vec"
+ targ_selvecs="bfd_elf32_i386_nacl_vec bfd_elf64_x86_64_nacl_vec bfd_elf32_bigarm_nacl_vec bfd_elf32_littlearm_nacl_vec"
+ targ_archs="$targ_archs bfd_arm_arch"
want64=true
;;
x86_64-*-mingw* | x86_64-*-pe | x86_64-*-pep)
bfd_elf32_bfinfdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_bigarc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
- bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
+ bfd_elf32_bigarm_nacl_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigarm_symbian_vec)
- tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigarm_vxworks_vec)
- tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_bigmips_vxworks_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_little_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_littlearc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_symbian_vec)
- tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlearm_vxworks_vec)
- tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
- bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
+ bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
+ bfd_elf32_littlearm_nacl_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_littlemips_vxworks_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_bfinfdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_bigarc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
- bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
+ bfd_elf32_bigarm_nacl_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigarm_symbian_vec)
- tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigarm_vxworks_vec)
- tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_bigmips_vxworks_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_little_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_littlearc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_symbian_vec)
- tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlearm_vxworks_vec)
- tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
- bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
+ tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
+ bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
+ bfd_elf32_littlearm_nacl_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_littlemips_vxworks_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
#include "libiberty.h"
#include "libbfd.h"
#include "elf-bfd.h"
+#include "elf-nacl.h"
#include "elf-vxworks.h"
#include "elf/arm.h"
#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
static const unsigned long tls_trampoline [] =
- {
- 0xe08e0000, /* add r0, lr, r0 */
- 0xe5901004, /* ldr r1, [r0,#4] */
- 0xe12fff11, /* bx r1 */
- };
+{
+ 0xe08e0000, /* add r0, lr, r0 */
+ 0xe5901004, /* ldr r1, [r0,#4] */
+ 0xe12fff11, /* bx r1 */
+};
static const unsigned long dl_tlsdesc_lazy_trampoline [] =
- {
- 0xe52d2004, /* push {r2} */
- 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
- 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
- 0xe79f2002, /* 1: ldr r2, [pc, r2] */
- 0xe081100f, /* 2: add r1, pc */
- 0xe12fff12, /* bx r2 */
- 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
+{
+ 0xe52d2004, /* push {r2} */
+ 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
+ 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
+ 0xe79f2002, /* 1: ldr r2, [pc, r2] */
+ 0xe081100f, /* 2: add r1, pc */
+ 0xe12fff12, /* bx r2 */
+ 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
+ dl_tlsdesc_lazy_resolver(GOT) */
- 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
- };
+ 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
+};
#ifdef FOUR_WORD_PLT
called before the relocation has been set up calls the dynamic
linker first. */
static const bfd_vma elf32_arm_plt0_entry [] =
- {
- 0xe52de004, /* str lr, [sp, #-4]! */
- 0xe59fe010, /* ldr lr, [pc, #16] */
- 0xe08fe00e, /* add lr, pc, lr */
- 0xe5bef008, /* ldr pc, [lr, #8]! */
- };
+{
+ 0xe52de004, /* str lr, [sp, #-4]! */
+ 0xe59fe010, /* ldr lr, [pc, #16] */
+ 0xe08fe00e, /* add lr, pc, lr */
+ 0xe5bef008, /* ldr pc, [lr, #8]! */
+};
/* Subsequent entries in a procedure linkage table look like
this. */
static const bfd_vma elf32_arm_plt_entry [] =
- {
- 0xe28fc600, /* add ip, pc, #NN */
- 0xe28cca00, /* add ip, ip, #NN */
- 0xe5bcf000, /* ldr pc, [ip, #NN]! */
- 0x00000000, /* unused */
- };
+{
+ 0xe28fc600, /* add ip, pc, #NN */
+ 0xe28cca00, /* add ip, ip, #NN */
+ 0xe5bcf000, /* ldr pc, [ip, #NN]! */
+ 0x00000000, /* unused */
+};
#else
called before the relocation has been set up calls the dynamic
linker first. */
static const bfd_vma elf32_arm_plt0_entry [] =
- {
- 0xe52de004, /* str lr, [sp, #-4]! */
- 0xe59fe004, /* ldr lr, [pc, #4] */
- 0xe08fe00e, /* add lr, pc, lr */
- 0xe5bef008, /* ldr pc, [lr, #8]! */
- 0x00000000, /* &GOT[0] - . */
- };
+{
+ 0xe52de004, /* str lr, [sp, #-4]! */
+ 0xe59fe004, /* ldr lr, [pc, #4] */
+ 0xe08fe00e, /* add lr, pc, lr */
+ 0xe5bef008, /* ldr pc, [lr, #8]! */
+ 0x00000000, /* &GOT[0] - . */
+};
/* Subsequent entries in a procedure linkage table look like
this. */
static const bfd_vma elf32_arm_plt_entry [] =
- {
- 0xe28fc600, /* add ip, pc, #0xNN00000 */
- 0xe28cca00, /* add ip, ip, #0xNN000 */
- 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
- };
+{
+ 0xe28fc600, /* add ip, pc, #0xNN00000 */
+ 0xe28cca00, /* add ip, ip, #0xNN000 */
+ 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
+};
#endif
/* The format of the first entry in the procedure linkage table
for a VxWorks executable. */
static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
- {
- 0xe52dc008, /* str ip,[sp,#-8]! */
- 0xe59fc000, /* ldr ip,[pc] */
- 0xe59cf008, /* ldr pc,[ip,#8] */
- 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
- };
+{
+ 0xe52dc008, /* str ip,[sp,#-8]! */
+ 0xe59fc000, /* ldr ip,[pc] */
+ 0xe59cf008, /* ldr pc,[ip,#8] */
+ 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
+};
/* The format of subsequent entries in a VxWorks executable. */
static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
- {
- 0xe59fc000, /* ldr ip,[pc] */
- 0xe59cf000, /* ldr pc,[ip] */
- 0x00000000, /* .long @got */
- 0xe59fc000, /* ldr ip,[pc] */
- 0xea000000, /* b _PLT */
- 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
- };
+{
+ 0xe59fc000, /* ldr ip,[pc] */
+ 0xe59cf000, /* ldr pc,[ip] */
+ 0x00000000, /* .long @got */
+ 0xe59fc000, /* ldr ip,[pc] */
+ 0xea000000, /* b _PLT */
+ 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
+};
/* The format of entries in a VxWorks shared library. */
static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
- {
- 0xe59fc000, /* ldr ip,[pc] */
- 0xe79cf009, /* ldr pc,[ip,r9] */
- 0x00000000, /* .long @got */
- 0xe59fc000, /* ldr ip,[pc] */
- 0xe599f008, /* ldr pc,[r9,#8] */
- 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
- };
+{
+ 0xe59fc000, /* ldr ip,[pc] */
+ 0xe79cf009, /* ldr pc,[ip,r9] */
+ 0x00000000, /* .long @got */
+ 0xe59fc000, /* ldr ip,[pc] */
+ 0xe599f008, /* ldr pc,[r9,#8] */
+ 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
+};
/* An initial stub used if the PLT entry is referenced from Thumb code. */
#define PLT_THUMB_STUB_SIZE 4
static const bfd_vma elf32_arm_plt_thumb_stub [] =
- {
- 0x4778, /* bx pc */
- 0x46c0 /* nop */
- };
+{
+ 0x4778, /* bx pc */
+ 0x46c0 /* nop */
+};
/* The entries in a PLT when using a DLL-based target with multiple
address spaces. */
static const bfd_vma elf32_arm_symbian_plt_entry [] =
- {
- 0xe51ff004, /* ldr pc, [pc, #-4] */
- 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
- };
+{
+ 0xe51ff004, /* ldr pc, [pc, #-4] */
+ 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
+};
+
+/* The first entry in a procedure linkage table looks like
+ this. It is set up so that any shared library function that is
+ called before the relocation has been set up calls the dynamic
+ linker first. */
+static const bfd_vma elf32_arm_nacl_plt0_entry [] =
+{
+ /* First bundle: */
+ 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
+ 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
+ 0xe08cc00f, /* add ip, ip, pc */
+ 0xe52dc008, /* str ip, [sp, #-8]! */
+ /* Second bundle: */
+ 0xe7dfcf1f, /* bfc ip, #30, #2 */
+ 0xe59cc000, /* ldr ip, [ip] */
+ 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
+ 0xe12fff1c, /* bx ip */
+ /* Third bundle: */
+ 0xe320f000, /* nop */
+ 0xe320f000, /* nop */
+ 0xe320f000, /* nop */
+ /* .Lplt_tail: */
+ 0xe50dc004, /* str ip, [sp, #-4] */
+ /* Fourth bundle: */
+ 0xe7dfcf1f, /* bfc ip, #30, #2 */
+ 0xe59cc000, /* ldr ip, [ip] */
+ 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
+ 0xe12fff1c, /* bx ip */
+};
+#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
+
+/* Subsequent entries in a procedure linkage table look like this. */
+static const bfd_vma elf32_arm_nacl_plt_entry [] =
+{
+ 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
+ 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
+ 0xe08cc00f, /* add ip, ip, pc */
+ 0xea000000, /* b .Lplt_tail */
+};
#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
enum stub_insn_type
- {
- THUMB16_TYPE = 1,
- THUMB32_TYPE,
- ARM_TYPE,
- DATA_TYPE
- };
+{
+ THUMB16_TYPE = 1,
+ THUMB32_TYPE,
+ ARM_TYPE,
+ DATA_TYPE
+};
#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
/* A bit of a hack. A Thumb conditional branch, in which the proper condition
typedef struct
{
- bfd_vma data;
- enum stub_insn_type type;
- unsigned int r_type;
- int reloc_addend;
+ bfd_vma data;
+ enum stub_insn_type type;
+ unsigned int r_type;
+ int reloc_addend;
} insn_sequence;
/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
to reach the stub if necessary. */
static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
- {
- ARM_INSN(0xe51ff004), /* ldr pc, [pc, #-4] */
- DATA_WORD(0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
- };
+{
+ ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
+ DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
+};
/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
available. */
static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
- {
- ARM_INSN(0xe59fc000), /* ldr ip, [pc, #0] */
- ARM_INSN(0xe12fff1c), /* bx ip */
- DATA_WORD(0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
- };
+{
+ ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
+ ARM_INSN (0xe12fff1c), /* bx ip */
+ DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
+};
/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
- {
- THUMB16_INSN(0xb401), /* push {r0} */
- THUMB16_INSN(0x4802), /* ldr r0, [pc, #8] */
- THUMB16_INSN(0x4684), /* mov ip, r0 */
- THUMB16_INSN(0xbc01), /* pop {r0} */
- THUMB16_INSN(0x4760), /* bx ip */
- THUMB16_INSN(0xbf00), /* nop */
- DATA_WORD(0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
- };
+{
+ THUMB16_INSN (0xb401), /* push {r0} */
+ THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
+ THUMB16_INSN (0x4684), /* mov ip, r0 */
+ THUMB16_INSN (0xbc01), /* pop {r0} */
+ THUMB16_INSN (0x4760), /* bx ip */
+ THUMB16_INSN (0xbf00), /* nop */
+ DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
+};
/* V4T Thumb -> Thumb long branch stub. Using the stack is not
allowed. */
static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
- {
- THUMB16_INSN(0x4778), /* bx pc */
- THUMB16_INSN(0x46c0), /* nop */
- ARM_INSN(0xe59fc000), /* ldr ip, [pc, #0] */
- ARM_INSN(0xe12fff1c), /* bx ip */
- DATA_WORD(0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
- };
+{
+ THUMB16_INSN (0x4778), /* bx pc */
+ THUMB16_INSN (0x46c0), /* nop */
+ ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
+ ARM_INSN (0xe12fff1c), /* bx ip */
+ DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
+};
/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
available. */
static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
- {
- THUMB16_INSN(0x4778), /* bx pc */
- THUMB16_INSN(0x46c0), /* nop */
- ARM_INSN(0xe51ff004), /* ldr pc, [pc, #-4] */
- DATA_WORD(0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
- };
+{
+ THUMB16_INSN (0x4778), /* bx pc */
+ THUMB16_INSN (0x46c0), /* nop */
+ ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
+ DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
+};
/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
one, when the destination is close enough. */
static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
- {
- THUMB16_INSN(0x4778), /* bx pc */
- THUMB16_INSN(0x46c0), /* nop */
- ARM_REL_INSN(0xea000000, -8), /* b (X-8) */
- };
+{
+ THUMB16_INSN (0x4778), /* bx pc */
+ THUMB16_INSN (0x46c0), /* nop */
+ ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
+};
/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
blx to reach the stub if necessary. */
static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
- {
- ARM_INSN(0xe59fc000), /* ldr ip, [pc] */
- ARM_INSN(0xe08ff00c), /* add pc, pc, ip */
- DATA_WORD(0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
- };
+{
+ ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
+ ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
+ DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
+};
/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
blx to reach the stub if necessary. We can not add into pc;
it is not guaranteed to mode switch (different in ARMv6 and
ARMv7). */
static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
- {
- ARM_INSN(0xe59fc004), /* ldr ip, [pc, #4] */
- ARM_INSN(0xe08fc00c), /* add ip, pc, ip */
- ARM_INSN(0xe12fff1c), /* bx ip */
- DATA_WORD(0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
- };
+{
+ ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
+ ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
+ ARM_INSN (0xe12fff1c), /* bx ip */
+ DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
+};
/* V4T ARM -> ARM long branch stub, PIC. */
static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
- {
- ARM_INSN(0xe59fc004), /* ldr ip, [pc, #4] */
- ARM_INSN(0xe08fc00c), /* add ip, pc, ip */
- ARM_INSN(0xe12fff1c), /* bx ip */
- DATA_WORD(0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
- };
+{
+ ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
+ ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
+ ARM_INSN (0xe12fff1c), /* bx ip */
+ DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
+};
/* V4T Thumb -> ARM long branch stub, PIC. */
static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
- {
- THUMB16_INSN(0x4778), /* bx pc */
- THUMB16_INSN(0x46c0), /* nop */
- ARM_INSN(0xe59fc000), /* ldr ip, [pc, #0] */
- ARM_INSN(0xe08cf00f), /* add pc, ip, pc */
- DATA_WORD(0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
- };
+{
+ THUMB16_INSN (0x4778), /* bx pc */
+ THUMB16_INSN (0x46c0), /* nop */
+ ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
+ ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
+ DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
+};
/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
architectures. */
static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
- {
- THUMB16_INSN(0xb401), /* push {r0} */
- THUMB16_INSN(0x4802), /* ldr r0, [pc, #8] */
- THUMB16_INSN(0x46fc), /* mov ip, pc */
- THUMB16_INSN(0x4484), /* add ip, r0 */
- THUMB16_INSN(0xbc01), /* pop {r0} */
- THUMB16_INSN(0x4760), /* bx ip */
- DATA_WORD(0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
- };
+{
+ THUMB16_INSN (0xb401), /* push {r0} */
+ THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
+ THUMB16_INSN (0x46fc), /* mov ip, pc */
+ THUMB16_INSN (0x4484), /* add ip, r0 */
+ THUMB16_INSN (0xbc01), /* pop {r0} */
+ THUMB16_INSN (0x4760), /* bx ip */
+ DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
+};
/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
allowed. */
static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
- {
- THUMB16_INSN(0x4778), /* bx pc */
- THUMB16_INSN(0x46c0), /* nop */
- ARM_INSN(0xe59fc004), /* ldr ip, [pc, #4] */
- ARM_INSN(0xe08fc00c), /* add ip, pc, ip */
- ARM_INSN(0xe12fff1c), /* bx ip */
- DATA_WORD(0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
- };
+{
+ THUMB16_INSN (0x4778), /* bx pc */
+ THUMB16_INSN (0x46c0), /* nop */
+ ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
+ ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
+ ARM_INSN (0xe12fff1c), /* bx ip */
+ DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
+};
/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
{
- ARM_INSN(0xe59f1000), /* ldr r1, [pc] */
- ARM_INSN(0xe08ff001), /* add pc, pc, r1 */
- DATA_WORD(0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
+ ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
+ ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
+ DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
};
/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
{
- THUMB16_INSN(0x4778), /* bx pc */
- THUMB16_INSN(0x46c0), /* nop */
- ARM_INSN(0xe59f1000), /* ldr r1, [pc, #0] */
- ARM_INSN(0xe081f00f), /* add pc, r1, pc */
- DATA_WORD(0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
+ THUMB16_INSN (0x4778), /* bx pc */
+ THUMB16_INSN (0x46c0), /* nop */
+ ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
+ ARM_INSN (0xe081f00f), /* add pc, r1, pc */
+ DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
};
/* Cortex-A8 erratum-workaround stubs. */
can't use a conditional branch to reach this stub). */
static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
- {
- THUMB16_BCOND_INSN(0xd001), /* b<cond>.n true. */
- THUMB32_B_INSN(0xf000b800, -4), /* b.w insn_after_original_branch. */
- THUMB32_B_INSN(0xf000b800, -4) /* true: b.w original_branch_dest. */
- };
+{
+ THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
+ THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
+ THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
+};
/* Stub used for b.w and bl.w instructions. */
static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
- {
- THUMB32_B_INSN(0xf000b800, -4) /* b.w original_branch_dest. */
- };
+{
+ THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
+};
static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
- {
- THUMB32_B_INSN(0xf000b800, -4) /* b.w original_branch_dest. */
- };
+{
+ THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
+};
/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
instruction (which switches to ARM mode) to point to this stub. Jump to the
real destination using an ARM-mode branch. */
static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
- {
- ARM_REL_INSN(0xea000000, -8) /* b original_branch_dest. */
- };
+{
+ ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
+};
/* For each section group there can be a specially created linker section
to hold the stubs for that group. The name of the stub section is based
PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
create what appeared to be a linker stub section when it actually
contained user code/data. For example, consider this fragment:
-
+
const char * stubborn_problems[] = { "np" };
If this is compiled with "-fPIC -fdata-sections" then gcc produces a
DEF_STUB(a8_veneer_blx)
#define DEF_STUB(x) arm_stub_##x,
-enum elf32_arm_stub_type {
+enum elf32_arm_stub_type
+{
arm_stub_none,
DEF_STUBS
/* Note the first a8_veneer type */
} stub_def;
#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
-static const stub_def stub_definitions[] = {
+static const stub_def stub_definitions[] =
+{
{NULL, 0},
DEF_STUBS
};
relaxing which we can refresh easily, then create stubs for each potentially
erratum-triggering instruction once we've settled on a solution. */
-struct a8_erratum_fix {
+struct a8_erratum_fix
+{
bfd *input_bfd;
asection *section;
bfd_vma offset;
/* A table of relocs applied to branches which might trigger Cortex-A8
erratum. */
-struct a8_erratum_reloc {
+struct a8_erratum_reloc
+{
bfd_vma from;
bfd_vma destination;
struct elf32_arm_link_hash_entry *hash;
/* ARM-specific information about a PLT entry, over and above the usual
gotplt_union. */
-struct arm_plt_info {
+struct arm_plt_info
+{
/* We reference count Thumb references to a PLT entry separately,
so that we can emit the Thumb trampoline only if needed. */
bfd_signed_vma thumb_refcount;
};
/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
-struct arm_local_iplt_info {
+struct arm_local_iplt_info
+{
/* The information that is usually found in the generic ELF part of
the hash table entry. */
union gotplt_union root;
/* Arm ELF linker hash entry. */
struct elf32_arm_link_hash_entry
- {
- struct elf_link_hash_entry root;
+{
+ struct elf_link_hash_entry root;
- /* Track dynamic relocs copied for this symbol. */
- struct elf_dyn_relocs *dyn_relocs;
+ /* Track dynamic relocs copied for this symbol. */
+ struct elf_dyn_relocs *dyn_relocs;
- /* ARM-specific PLT information. */
- struct arm_plt_info plt;
+ /* ARM-specific PLT information. */
+ struct arm_plt_info plt;
#define GOT_UNKNOWN 0
#define GOT_NORMAL 1
#define GOT_TLS_IE 4
#define GOT_TLS_GDESC 8
#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
- unsigned int tls_type : 8;
+ unsigned int tls_type : 8;
- /* True if the symbol's PLT entry is in .iplt rather than .plt. */
- unsigned int is_iplt : 1;
+ /* True if the symbol's PLT entry is in .iplt rather than .plt. */
+ unsigned int is_iplt : 1;
- unsigned int unused : 23;
+ unsigned int unused : 23;
- /* Offset of the GOTPLT entry reserved for the TLS descriptor,
- starting at the end of the jump table. */
- bfd_vma tlsdesc_got;
+ /* Offset of the GOTPLT entry reserved for the TLS descriptor,
+ starting at the end of the jump table. */
+ bfd_vma tlsdesc_got;
- /* The symbol marking the real symbol location for exported thumb
- symbols with Arm stubs. */
- struct elf_link_hash_entry *export_glue;
+ /* The symbol marking the real symbol location for exported thumb
+ symbols with Arm stubs. */
+ struct elf_link_hash_entry *export_glue;
- /* A pointer to the most recently used stub hash entry against this
+ /* A pointer to the most recently used stub hash entry against this
symbol. */
- struct elf32_arm_stub_hash_entry *stub_cache;
- };
+ struct elf32_arm_stub_hash_entry *stub_cache;
+};
/* Traverse an arm ELF linker hash table. */
#define elf32_arm_link_hash_traverse(table, func, info) \
/* True if the target system is Symbian OS. */
int symbian_p;
+ /* True if the target system is Native Client. */
+ int nacl_p;
+
/* True if the target uses REL relocations. */
int use_rel;
/* The offset into sgot of the GOT entry used by the PLT entry
above. */
- bfd_vma dt_tlsdesc_got;
+ bfd_vma dt_tlsdesc_got;
/* Offset in .plt section of tls_arm_trampoline. */
bfd_vma tls_trampoline;
bfd *dynobj;
asection *s;
flagword flags;
-
+
htab = elf32_arm_hash_table (info);
dynobj = htab->root.dynobj;
bed = get_elf_backend_data (dynobj);
ret->use_blx = 0;
ret->vxworks_p = 0;
ret->symbian_p = 0;
+ ret->nacl_p = 0;
ret->use_rel = 1;
ret->sym_cache.abfd = NULL;
ret->obfd = abfd;
else
splt = globals->root.splt;
if (splt != NULL)
- {
+ {
use_plt = 1;
/* Note when dealing with PLT entries: the main PLT stub is in
}
/* Find or create a stub section. Returns a pointer to the stub section, and
- the section to which the stub section will be attached (in *LINK_SEC_P).
+ the section to which the stub section will be attached (in *LINK_SEC_P).
LINK_SEC_P may be NULL. */
static asection *
}
htab->stub_group[section->id].stub_sec = stub_sec;
}
-
+
if (link_sec_p)
*link_sec_p = link_sec;
-
+
return stub_sec;
}
model, return the new reloc type. */
static unsigned
-elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
+elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
struct elf_link_hash_entry *h)
{
int is_local = (h == NULL);
if (info->shared || (h && h->root.type == bfd_link_hash_undefweak))
return r_type;
- /* We do not support relaxations for Old TLS models. */
+ /* We do not support relaxations for Old TLS models. */
switch (r_type)
{
case R_ARM_TLS_GOTDESC:
case arm_stub_long_branch_v4t_thumb_tls_pic:
case arm_stub_a8_veneer_blx:
return 4;
-
+
default:
abort (); /* Should be unreachable. */
}
free (internal_relocs);
goto error_ret_free_local;
}
-
+
hash = NULL;
if (r_indx >= symtab_hdr->sh_info)
hash = elf32_arm_hash_entry
(elf_sym_hashes (input_bfd)
[r_indx - symtab_hdr->sh_info]);
-
+
/* Only look for stubs on branch instructions, or
non-relaxed TLSCALL */
if ((r_type != (unsigned int) R_ARM_CALL)
sym_value = 0;
destination = 0;
sym_name = NULL;
-
+
if (r_type == (unsigned int) R_ARM_TLS_CALL
|| r_type == (unsigned int) R_ARM_THM_TLS_CALL)
{
.arm mov lr, pc
b func bx r6
.arm
- ;; back_to_thumb
+ ;; back_to_thumb
ldmia r13! {r6, lr}
- bx lr
+ bx lr
__func_addr:
.word func */
{
int cpu_arch;
- cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
+ cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
Tag_CPU_arch);
if (globals->fix_arm1176)
}
}
+static bfd_vma
+arm_movw_immediate (bfd_vma value)
+{
+ return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
+}
+
+static bfd_vma
+arm_movt_immediate (bfd_vma value)
+{
+ return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
+}
+
/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
the entry lives in .iplt and resolves to (*SYM_VALUE)().
Otherwise, DYNINDX is the index of the symbol in the dynamic
rel.r_addend = 0;
SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
}
+ else if (htab->nacl_p)
+ {
+ /* Calculate the displacement between the PLT slot and the
+ common tail that's part of the special initial PLT slot. */
+ bfd_vma tail_displacement
+ = ((splt->output_section->vma + splt->output_offset
+ + ARM_NACL_PLT_TAIL_OFFSET)
+ - (plt_address + htab->plt_entry_size + 4));
+ BFD_ASSERT ((tail_displacement & 3) == 0);
+ tail_displacement >>= 2;
+
+ BFD_ASSERT ((tail_displacement & 0xff000000) == 0
+ || (-tail_displacement & 0xff000000) == 0);
+
+ /* Calculate the displacement between the PLT slot and the entry
+ in the GOT. The offset accounts for the value produced by
+ adding to pc in the penultimate instruction of the PLT stub. */
+ got_displacement = got_address - (plt_address + htab->plt_entry_size);
+
+ /* NaCl does not support interworking at all. */
+ BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
+
+ put_arm_insn (htab, output_bfd,
+ elf32_arm_nacl_plt_entry[0]
+ | arm_movw_immediate (got_displacement),
+ ptr + 0);
+ put_arm_insn (htab, output_bfd,
+ elf32_arm_nacl_plt_entry[1]
+ | arm_movt_immediate (got_displacement),
+ ptr + 4);
+ put_arm_insn (htab, output_bfd,
+ elf32_arm_nacl_plt_entry[2],
+ ptr + 8);
+ put_arm_insn (htab, output_bfd,
+ elf32_arm_nacl_plt_entry[3]
+ | (tail_displacement & 0x00ffffff),
+ ptr + 12);
+ }
else
{
/* Calculate the displacement between the PLT slot and the
the pre-relaxed code. It would be nice if the relocs were updated
to match the optimization. */
-static bfd_reloc_status_type
+static bfd_reloc_status_type
elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
- bfd *input_bfd, asection *input_sec, bfd_byte *contents,
+ bfd *input_bfd, asection *input_sec, bfd_byte *contents,
Elf_Internal_Rela *rel, unsigned long is_local)
{
unsigned long insn;
-
+
switch (ELF32_R_TYPE (rel->r_info))
{
default:
return bfd_reloc_notsupported;
-
+
case R_ARM_TLS_GOTDESC:
if (is_local)
insn = 0;
return bfd_reloc_notsupported;
}
break;
-
+
case R_ARM_TLS_DESCSEQ:
/* arm insn. */
insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
insn = is_local ? 0xe1a00000 : 0xe79f0000;
bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
break;
-
+
case R_ARM_THM_TLS_CALL:
/* GD->IE relaxation */
if (!is_local)
else
/* nop; nop */
insn = 0xbf00bf00;
-
+
bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
break;
}
/* Linker relaxations happens from one of the
- R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
+ R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
if (ELF32_R_TYPE(rel->r_info) != r_type)
- tls_type = GOT_TLS_IE;
+ tls_type = GOT_TLS_IE;
BFD_ASSERT (tls_type != GOT_UNKNOWN);
+ globals->root.sgotplt->output_offset
+ offplt
+ globals->sgotplt_jump_table_size);
-
+
outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
sreloc = globals->root.srelplt;
loc = sreloc->contents;
!h ? value - elf_hash_table (info)->tls_sec->vma
: info->flags & DF_BIND_NOW ? 0
: 0x80000000 | ELF32_R_SYM (outrel.r_info),
- globals->root.sgotplt->contents + offplt +
- globals->sgotplt_jump_table_size);
-
+ globals->root.sgotplt->contents + offplt
+ + globals->sgotplt_jump_table_size);
+
/* Second word in the relocation is always zero. */
bfd_put_32 (output_bfd, 0,
- globals->root.sgotplt->contents + offplt +
- globals->sgotplt_jump_table_size + 4);
+ globals->root.sgotplt->contents + offplt
+ + globals->sgotplt_jump_table_size + 4);
}
if (tls_type & GOT_TLS_GD)
{
if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
{
unsigned long inst;
-
- offset -= (input_section->output_section->vma +
- input_section->output_offset + rel->r_offset + 8);
+
+ offset -= (input_section->output_section->vma
+ + input_section->output_offset
+ + rel->r_offset + 8);
inst = offset >> 2;
inst &= 0x00ffffff;
unsigned upper_insn, lower_insn;
unsigned neg;
- offset -= (input_section->output_section->vma +
- input_section->output_offset
+ offset -= (input_section->output_section->vma
+ + input_section->output_offset
+ rel->r_offset + 4);
-
+
if (stub_type != arm_stub_none
&& arm_stub_is_thumb (stub_type))
{
{
unsigned long data, insn;
unsigned thumb;
-
+
data = bfd_get_32 (input_bfd, hit_data);
thumb = data & 1;
data &= ~1u;
-
+
if (thumb)
{
insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
case 0xe0: /* add */
value = -8;
break;
-
+
default:
(*_bfd_error_handler)
(_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
return bfd_reloc_notsupported;
}
}
-
+
value += ((globals->root.sgotplt->output_section->vma
+ globals->root.sgotplt->output_offset + off)
- (input_section->output_section->vma
rel->r_offset, TRUE))
return FALSE;
}
-
+
if (globals->use_rel)
{
relocation = (sec->output_section->vma
both in relaxed and non-relaxed cases */
if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
|| (IS_ARM_TLS_GNU_RELOC (r_type)
- && !((h ? elf32_arm_hash_entry (h)->tls_type :
+ && !((h ? elf32_arm_hash_entry (h)->tls_type :
elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
& GOT_TLS_GDESC)))
{
}
else
r = bfd_reloc_continue;
-
+
if (r == bfd_reloc_continue)
r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
input_section, contents, rel,
{
arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
xmalloc (sizeof (arm_unwind_table_edit));
-
+
new_edit->type = type;
new_edit->linked_section = linked_section;
new_edit->index = tindex;
-
+
if (tindex > 0)
{
new_edit->next = NULL;
/* Scan .ARM.exidx tables, and create a list describing edits which should be
made to those tables, such that:
-
+
1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
codes which have been inlined into the index).
If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
The edits are applied when the tables are written
- (in elf32_arm_write_section).
-*/
+ (in elf32_arm_write_section). */
bfd_boolean
elf32_arm_fix_exidx_coverage (asection **text_section_order,
for (inp = info->input_bfds; inp != NULL; inp = inp->link_next)
{
asection *sec;
-
+
for (sec = inp->sections; sec != NULL; sec = sec->next)
{
struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
-
+
if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
continue;
-
+
if (elf_sec->linked_to)
{
Elf_Internal_Shdr *linked_hdr
hdr = &elf_section_data (exidx_sec)->this_hdr;
if (hdr->sh_type != SHT_ARM_EXIDX)
continue;
-
+
exidx_arm_data = get_arm_elf_section_data (exidx_sec);
if (exidx_arm_data == NULL)
continue;
-
+
ibfd = exidx_sec->owner;
-
+
if (hdr->contents != NULL)
contents = hdr->contents;
else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
/* Record edits to be applied later (in elf32_arm_write_section). */
exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
-
+
if (deleted_exidx_bytes > 0)
adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
{
_bfd_error_handler
(_("%B has has both the current and legacy "
- "Tag_MPextension_use attributes"),
+ "Tag_MPextension_use attributes"),
ibfd);
result = FALSE;
}
symtab_hdr = & elf_symtab_hdr (abfd);
sym_hashes = elf_sym_hashes (abfd);
nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
-
+
rel_end = relocs + sec->reloc_count;
for (rel = relocs; rel < rel_end; rel++)
{
switch (r_type)
{
case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
-
+
case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
-
+
case R_ARM_TLS_GOTDESC:
case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
tls_type = GOT_TLS_GDESC; break;
-
+
default: tls_type = GOT_NORMAL; break;
}
if (tls_type & GOT_TLS_GD)
elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
- if (tls_type & GOT_TLS_GDESC)
+ if (tls_type & GOT_TLS_GDESC)
{
elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
/* GDESC needs a trampoline to jump to. */
/* Only GD needs it. GDESC just emits one relocation per
2 entries. */
- if ((tls_type & GOT_TLS_GD) && indx != 0)
+ if ((tls_type & GOT_TLS_GD) && indx != 0)
elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
}
else if (!SYMBOL_REFERENCES_LOCAL (info, h))
{
if (htab->root.splt->size == 0)
htab->root.splt->size += htab->plt_header_size;
-
+
htab->tls_trampoline = htab->root.splt->size;
htab->root.splt->size += htab->plt_entry_size;
-
+
/* If we're not using lazy TLS relocations, don't generate the
PLT and GOT entries they require. */
if (!(info->flags & DF_BIND_NOW))
return FALSE;
if (htab->dt_tlsdesc_plt &&
- (!add_dynamic_entry (DT_TLSDESC_PLT,0)
+ (!add_dynamic_entry (DT_TLSDESC_PLT,0)
|| !add_dynamic_entry (DT_TLSDESC_GOT,0)))
- return FALSE;
+ return FALSE;
}
if (relocs)
tls_sec, 0, NULL, FALSE,
bed->collect, &bh)))
return FALSE;
-
+
tlsbase->type = STT_TLS;
tlsbase = (struct elf_link_hash_entry *)bh;
tlsbase->def_regular = 1;
const unsigned long *template, unsigned count)
{
unsigned ix;
-
+
for (ix = 0; ix != count; ix++)
{
unsigned long insn = template[ix];
SWAP_RELOC_OUT (htab) (output_bfd, &rel,
htab->srelplt2->contents);
}
+ else if (htab->nacl_p)
+ {
+ unsigned int i;
+
+ got_displacement = got_address + 8 - (plt_address + 16);
+
+ put_arm_insn (htab, output_bfd,
+ elf32_arm_nacl_plt0_entry[0]
+ | arm_movw_immediate (got_displacement),
+ splt->contents + 0);
+ put_arm_insn (htab, output_bfd,
+ elf32_arm_nacl_plt0_entry[1]
+ | arm_movt_immediate (got_displacement),
+ splt->contents + 4);
+ for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
+ put_arm_insn (htab, output_bfd,
+ elf32_arm_nacl_plt0_entry[i],
+ splt->contents + (i * 4));
+ }
else
{
got_displacement = got_address - (plt_address + 16);
bfd_vma plt_address
= splt->output_section->vma + splt->output_offset;
- arm_put_trampoline (htab, output_bfd,
+ arm_put_trampoline (htab, output_bfd,
splt->contents + htab->dt_tlsdesc_plt,
dl_tlsdesc_lazy_trampoline, 6);
if (htab->tls_trampoline)
{
- arm_put_trampoline (htab, output_bfd,
+ arm_put_trampoline (htab, output_bfd,
splt->contents + htab->tls_trampoline,
tls_trampoline, 3);
#ifdef FOUR_WORD_PLT
bfd_put_32 (output_bfd, 0x00000000,
splt->contents + htab->tls_trampoline + 12);
-#endif
+#endif
}
if (htab->vxworks_p && !info->shared && htab->root.splt->size > 0)
if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
return FALSE;
}
+ else if (htab->nacl_p)
+ {
+ if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
+ return FALSE;
+ }
else
{
bfd_boolean thumb_stub_p;
return FALSE;
}
}
+ else if (htab->nacl_p)
+ {
+ if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
+ return FALSE;
+ }
else if (!htab->symbian_p)
{
if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
/* Mapping symbols for the lazy tls trampoline. */
if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
return FALSE;
-
+
if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
htab->dt_tlsdesc_plt + 24))
return FALSE;
if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
htab->tls_trampoline + 12))
return FALSE;
-#endif
+#endif
}
-
+
return TRUE;
}
{
unsigned long first_word = bfd_get_32 (output_bfd, from);
unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
-
+
/* High bit of first word is supposed to be zero. */
if ((first_word & 0x80000000ul) == 0)
first_word = offset_prel31 (first_word, offset);
-
+
/* If the high bit of the first word is clear, and the bit pattern is not 0x1
(EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
second_word = offset_prel31 (second_word, offset);
-
+
bfd_put_32 (output_bfd, first_word, to);
bfd_put_32 (output_bfd, second_word, to + 4);
}
/* Data for make_branch_to_a8_stub(). */
-struct a8_branch_to_stub_data {
+struct a8_branch_to_stub_data
+{
asection *writing_section;
bfd_byte *contents;
};
if (edit_node)
{
unsigned int edit_index = edit_node->index;
-
+
if (in_index < edit_index && in_index * 8 < input_size)
{
copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
in_index++;
add_to_offsets += 8;
break;
-
+
case INSERT_EXIDX_CANTUNWIND_AT_END:
{
asection *text_sec = edit_node->linked_section;
}
break;
}
-
+
edit_node = edit_node->next;
}
}
#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
#define bfd_elf32_bfd_link_hash_table_free elf32_arm_hash_table_free
#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
-#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
+#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
#undef elf_backend_obj_attrs_section_type
#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
-#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
-#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
+#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
+#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
+
+#include "elf32-target.h"
+
+/* Native Client targets. */
+
+#undef TARGET_LITTLE_SYM
+#define TARGET_LITTLE_SYM bfd_elf32_littlearm_nacl_vec
+#undef TARGET_LITTLE_NAME
+#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
+#undef TARGET_BIG_SYM
+#define TARGET_BIG_SYM bfd_elf32_bigarm_nacl_vec
+#undef TARGET_BIG_NAME
+#define TARGET_BIG_NAME "elf32-bigarm-nacl"
+
+/* Like elf32_arm_link_hash_table_create -- but overrides
+ appropriately for NaCl. */
+
+static struct bfd_link_hash_table *
+elf32_arm_nacl_link_hash_table_create (bfd *abfd)
+{
+ struct bfd_link_hash_table *ret;
+
+ ret = elf32_arm_link_hash_table_create (abfd);
+ if (ret)
+ {
+ struct elf32_arm_link_hash_table *htab
+ = (struct elf32_arm_link_hash_table *) ret;
+
+ htab->nacl_p = 1;
+
+ htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
+ htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
+ }
+ return ret;
+}
+
+/* Since NaCl doesn't use the ARM-specific unwind format, we don't
+ really need to use elf32_arm_modify_segment_map. But we do it
+ anyway just to reduce gratuitous differences with the stock ARM backend. */
+
+static bfd_boolean
+elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
+{
+ return (elf32_arm_modify_segment_map (abfd, info)
+ && nacl_modify_segment_map (abfd, info));
+}
+
+#undef elf32_bed
+#define elf32_bed elf32_arm_nacl_bed
+#undef bfd_elf32_bfd_link_hash_table_create
+#define bfd_elf32_bfd_link_hash_table_create \
+ elf32_arm_nacl_link_hash_table_create
+#undef elf_backend_plt_alignment
+#define elf_backend_plt_alignment 4
+#undef elf_backend_modify_segment_map
+#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
+#undef elf_backend_modify_program_headers
+#define elf_backend_modify_program_headers nacl_modify_program_headers
+
+#undef ELF_MAXPAGESIZE
+#define ELF_MAXPAGESIZE 0x10000
#include "elf32-target.h"
+/* Reset to defaults. */
+#undef elf_backend_plt_alignment
+#undef elf_backend_modify_segment_map
+#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
+#undef elf_backend_modify_program_headers
+
/* VxWorks Targets. */
#undef TARGET_LITTLE_SYM
extern const bfd_target bfd_elf32_big_generic_vec;
extern const bfd_target bfd_elf32_bigarc_vec;
extern const bfd_target bfd_elf32_bigarm_vec;
+extern const bfd_target bfd_elf32_bigarm_nacl_vec;
extern const bfd_target bfd_elf32_bigarm_symbian_vec;
extern const bfd_target bfd_elf32_bigarm_vxworks_vec;
extern const bfd_target bfd_elf32_bigmips_vec;
extern const bfd_target bfd_elf32_little_generic_vec;
extern const bfd_target bfd_elf32_littlearc_vec;
extern const bfd_target bfd_elf32_littlearm_vec;
+extern const bfd_target bfd_elf32_littlearm_nacl_vec;
extern const bfd_target bfd_elf32_littlearm_symbian_vec;
extern const bfd_target bfd_elf32_littlearm_vxworks_vec;
extern const bfd_target bfd_elf32_littlemips_vec;
+2012-04-12 Roland McGrath <mcgrathr@google.com>
+
+ * configure.tgt (arm-*-nacl*): Match it.
+ * config/te-nacl.h (FPU_DEFAULT, EABI_DEFAULT): Define.
+ (LOCAL_LABELS_DOLLAR): Define.
+ * config/tc-arm.c (elf32_arm_target_format) [TE_NACL]:
+ Use nacl format variants.
+
2012-04-12 Jie Zhang <jie@codesourcery.com>
Meador Inge <meadori@codesourcery.com>
return (target_big_endian
? "elf32-bigarm-vxworks"
: "elf32-littlearm-vxworks");
+#elif defined (TE_NACL)
+ return (target_big_endian
+ ? "elf32-bigarm-nacl"
+ : "elf32-littlearm-nacl");
#else
if (target_big_endian)
return "elf32-bigarm";
02110-1301, USA. */
#define TE_NACL
+
+#define LOCAL_LABELS_DOLLAR 1
#define LOCAL_LABELS_FB 1
+/* These are for ARM but don't hurt other CPU targets.
+ They match the settings from te-armeabi.h; NaCl/ARM is based on EABI. */
+#define FPU_DEFAULT FPU_ARCH_VFP
+#define EABI_DEFAULT EF_ARM_EABI_VER5
+
#include "obj-format.h"
arm-*-linux-*) fmt=elf em=linux ;;
arm-*-uclinux*eabi*) fmt=elf em=armlinuxeabi ;;
arm-*-uclinux*) fmt=elf em=linux ;;
+ arm-*-nacl*) fmt=elf em=nacl ;;
arm-*-netbsdelf*) fmt=elf em=nbsd ;;
arm-*-*n*bsd*) fmt=aout em=nbsd ;;
arm-*-nto*) fmt=elf ;;
+2012-04-12 Roland McGrath <mcgrathr@google.com>
+
+ * gas/elf/elf.exp (run_elf_list_test): Treat arm-*-nacl* targets
+ as -armeabi.
+
+ * gas/arm/any-idiv.d: Match *-*-nacl* targets too.
+ * gas/arm/arch4t.d: Likewise.
+ * gas/arm/arch4t-eabi.d: Likewise.
+ * gas/arm/attr-any-armv4t.d: Likewise.
+ * gas/arm/attr-any-thumbv6.d: Likewise.
+ * gas/arm/attr-cpu-directive.d: Likewise.
+ * gas/arm/attr-default.d: Likewise.
+ * gas/arm/attr-march-all.d: Likewise.
+ * gas/arm/attr-march-armv1.d: Likewise.
+ * gas/arm/attr-march-armv2a.d: Likewise.
+ * gas/arm/attr-march-armv2.d: Likewise.
+ * gas/arm/attr-march-armv2s.d: Likewise.
+ * gas/arm/attr-march-armv3.d: Likewise.
+ * gas/arm/attr-march-armv3m.d: Likewise.
+ * gas/arm/attr-march-armv4.d: Likewise.
+ * gas/arm/attr-march-armv4t.d: Likewise.
+ * gas/arm/attr-march-armv4txm.d: Likewise.
+ * gas/arm/attr-march-armv4xm.d: Likewise.
+ * gas/arm/attr-march-armv5.d: Likewise.
+ * gas/arm/attr-march-armv5t.d: Likewise.
+ * gas/arm/attr-march-armv5te.d: Likewise.
+ * gas/arm/attr-march-armv5tej.d: Likewise.
+ * gas/arm/attr-march-armv5texp.d: Likewise.
+ * gas/arm/attr-march-armv5txm.d: Likewise.
+ * gas/arm/attr-march-armv6.d: Likewise.
+ * gas/arm/attr-march-armv6j.d: Likewise.
+ * gas/arm/attr-march-armv6k.d: Likewise.
+ * gas/arm/attr-march-armv6k+sec.d: Likewise.
+ * gas/arm/attr-march-armv6kt2.d: Likewise.
+ * gas/arm/attr-march-armv6-m.d: Likewise.
+ * gas/arm/attr-march-armv6-m+os.d: Likewise.
+ * gas/arm/attr-march-armv6s-m.d: Likewise.
+ * gas/arm/attr-march-armv6t2.d: Likewise.
+ * gas/arm/attr-march-armv6z.d: Likewise.
+ * gas/arm/attr-march-armv6zk.d: Likewise.
+ * gas/arm/attr-march-armv6zkt2.d: Likewise.
+ * gas/arm/attr-march-armv6zt2.d: Likewise.
+ * gas/arm/attr-march-armv7-a.d: Likewise.
+ * gas/arm/attr-march-armv7a.d: Likewise.
+ * gas/arm/attr-march-armv7-a+idiv.d: Likewise.
+ * gas/arm/attr-march-armv7-a+mp.d: Likewise.
+ * gas/arm/attr-march-armv7-a+sec.d: Likewise.
+ * gas/arm/attr-march-armv7-a+sec+virt.d: Likewise.
+ * gas/arm/attr-march-armv7-a+virt.d: Likewise.
+ * gas/arm/attr-march-armv7.d: Likewise.
+ * gas/arm/attr-march-armv7em.d: Likewise.
+ * gas/arm/attr-march-armv7-m.d: Likewise.
+ * gas/arm/attr-march-armv7m.d: Likewise.
+ * gas/arm/attr-march-armv7-r.d: Likewise.
+ * gas/arm/attr-march-armv7r.d: Likewise.
+ * gas/arm/attr-march-armv7-r+mp.d: Likewise.
+ * gas/arm/attr-march-iwmmxt2.d: Likewise.
+ * gas/arm/attr-march-iwmmxt.d: Likewise.
+ * gas/arm/attr-march-xscale.d: Likewise.
+ * gas/arm/attr-mcpu.d: Likewise.
+ * gas/arm/attr-mfpu-arm1020e.d: Likewise.
+ * gas/arm/attr-mfpu-arm1020t.d: Likewise.
+ * gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
+ * gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
+ * gas/arm/attr-mfpu-arm7500fe.d: Likewise.
+ * gas/arm/attr-mfpu-fpa10.d: Likewise.
+ * gas/arm/attr-mfpu-fpa11.d: Likewise.
+ * gas/arm/attr-mfpu-fpa.d: Likewise.
+ * gas/arm/attr-mfpu-fpe2.d: Likewise.
+ * gas/arm/attr-mfpu-fpe3.d: Likewise.
+ * gas/arm/attr-mfpu-fpe.d: Likewise.
+ * gas/arm/attr-mfpu-maverick.d: Likewise.
+ * gas/arm/attr-mfpu-neon.d: Likewise.
+ * gas/arm/attr-mfpu-neon-fp16.d: Likewise.
+ * gas/arm/attr-mfpu-softfpa.d: Likewise.
+ * gas/arm/attr-mfpu-softvfp.d: Likewise.
+ * gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
+ * gas/arm/attr-mfpu-vfp10.d: Likewise.
+ * gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
+ * gas/arm/attr-mfpu-vfp3.d: Likewise.
+ * gas/arm/attr-mfpu-vfp9.d: Likewise.
+ * gas/arm/attr-mfpu-vfp.d: Likewise.
+ * gas/arm/attr-mfpu-vfpv2.d: Likewise.
+ * gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
+ * gas/arm/attr-mfpu-vfpv3.d: Likewise.
+ * gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
+ * gas/arm/attr-mfpu-vfpv4.d: Likewise.
+ * gas/arm/attr-mfpu-vfpxd.d: Likewise.
+ * gas/arm/attr-names.d: Likewise.
+ * gas/arm/attr-order.d: Likewise.
+ * gas/arm/attr-override-cpu-directive.d: Likewise.
+ * gas/arm/attr-override-mcpu.d: Likewise.
+ * gas/arm/got_prel.d: Likewise.
+ * gas/arm/mapdir.d: Likewise.
+ * gas/arm/mapmisc.d: Likewise.
+ * gas/arm/mapsecs.d: Likewise.
+ * gas/arm/mapshort-eabi.d: Likewise.
+ * gas/arm/mapshort-elf.d: Likewise.
+ * gas/arm/mov-highregs-any.d: Likewise.
+ * gas/arm/mov-lowregs-any.d: Likewise.
+ * gas/arm/pr12198-1.d: Likewise.
+ * gas/arm/pr12198-2.d: Likewise.
+ * gas/arm/thumb.d: Likewise.
+ * gas/arm/thumb-eabi.d: Likewise.
+ * gas/arm/thumbrel.d: Likewise.
+
2012-04-12 Jie Zhang <jie@codesourcery.com>
Meador Inge <meadori@codesourcery.com>
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv4t
# objdump: -dr --prefix-addresses --show-raw-insn
# source: arch4t.s
-# target: *-*-*eabi *-*-symbianelf
+# target: *-*-*eabi *-*-symbianelf *-*-nacl*
.*: +file format .*arm.*
# as: -march=armv4t
# objdump: -dr --prefix-addresses --show-raw-insn
# EABI targets have their own variant.
-# not-target: *-*-*eabi *-*-symbianelf
+# not-target: *-*-*eabi *-*-symbianelf *-*-nacl*
.*: +file format .*arm.*
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=all
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv1
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv2
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv2a
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv2s
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv3
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv3m
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv4
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv4t
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv4txm
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv4xm
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv5
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv5t
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv5te
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv5tej
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv5texp
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv5txm
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6-m+os
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6-m
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6j
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6k+sec
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6k
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6kt2
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6-m
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6t2
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6z
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6zk
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6zkt2
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv6zt2
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-a+idiv
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-a+mp
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-a+sec+virt
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-a+sec
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-a+virt
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-a
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-m
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-r+mp
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7-r
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7a
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7e-m
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7m
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=armv7r
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=iwmmxt
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=iwmmxt2
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -march=xscale
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mcpu=cortex-a8 -mfpu=neon
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=arm1020e
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=arm1020t
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=arm1136jf-s
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=arm1136jfs
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=arm7500fe
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=fpa
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=fpa10
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=fpa11
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=fpe
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=fpe2
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=fpe3
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=maverick
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=neon-fp16
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=neon
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=softfpa
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=softvfp+vfp
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=softvfp
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfp
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfp10-r0
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfp10
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfp3
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfp9
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfpv2
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfpv3-d16
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfpv3
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfpv4-d16
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfpv4
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mfpu=vfpxd
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mcpu=cortex-a8
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# source: got_prel.s
# as: -march=armv5te -meabi=5
# readelf: -x 4 -r
-# target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf
+# target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl*
Relocation section '.rel.text.foo' at offset 0x3f0 contains 1 entries:
Offset Info Type Sym.Value Sym. Name
#objdump: --syms --special-syms -d
#name: ARM Mapping Symbols for .arm/.thumb
# This test is only valid on EABI based ports.
-#target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf
+#target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl*
#source: mapdir.s
#objdump: --syms --special-syms -d
#name: ARM Mapping Symbols for miscellaneous directives
# This test is only valid on EABI based ports.
-#target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf
+#target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl*
#source: mapmisc.s
#objdump: --syms --special-syms -d
#name: ARM Mapping Symbols with multiple sections
# This test is only valid on EABI based ports.
-#target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf
+#target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl*
#source: mapsecs.s
#objdump: --syms --special-syms -d
#name: ARM Mapping Symbols for .short (EABI version)
# This test is only valid on EABI based ports.
-#target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf
+#target: *-*-*eabi *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl*
#source: mapshort.s
# Test the generation and use of ARM ELF Mapping Symbols
#objdump: --syms --special-syms -d
#name: ARM Mapping Symbols for .short (ELF version)
# This test is only valid on ELF based ports.
-#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-*eabi *-*-syymbianelf *-*-linux-* *-*-vxworks *-*-elf
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-*eabi *-*-syymbianelf *-*-linux-* *-*-vxworks *-*-elf *-*-nacl*
#source: mapshort.s
# Test the generation and use of ARM ELF Mapping Symbols
# name: MOV highregs
# readelf: -A
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
Tag_CPU_arch: v4T
# name: MOV lowregs
# readelf: -A
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
Tag_CPU_arch: v6
Tag_THUMB_ISA_use: Thumb-1
-
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as:
# readelf: -A
# This test is only valid on EABI based ports.
-# target: *-*-*eabi
+# target: *-*-*eabi *-*-nacl*
Attribute Section: aeabi
File Attributes
# as: -mcpu=arm7t
# objdump: -dr --prefix-addresses --show-raw-insn
# source: thumb.s
-# target: *-*-*eabi *-*-symbianelf
+# target: *-*-*eabi *-*-symbianelf *-*-nacl*
.*: +file format .*arm.*
# objdump: -dr --prefix-addresses --show-raw-insn
# The arm-aout and arm-pe ports do not support Thumb branch relocations.
# EABI targets have their own variant.
-# not-target: *-*-*aout* *-*-pe *-*-*eabi *-*-symbianelf
+# not-target: *-*-*aout* *-*-pe *-*-*eabi *-*-symbianelf *-*-nacl*
.*: +file format .*arm.*
#objdump: -sr
# This test is only valid on EABI based ports.
-#target: *-*-*eabi *-*-symbianelf
+#target: *-*-*eabi *-*-symbianelf *-*-nacl*
.*: file format.*
if { ([istarget "*-*-*eabi"]
|| [istarget "*-*-linux-*"]
+ || [istarget "*-*-nacl*"]
|| [istarget "*-*-symbianelf"])} then {
set target_machine -armeabi
} else {
+2012-04-12 Roland McGrath <mcgrathr@google.com>
+
+ * configure.tgt (arm*-*-nacl*, arm*b-*-nacl*): Handle them.
+ * emulparams/armelf_nacl.sh: New file.
+ * emulparams/armelfb_nacl.sh: New file.
+ * Makefile.am (ALL_EMULATION_SOURCES): Add earmelf_nacl.c
+ and earmelfb_nacl.c here.
+ (earmelf_nacl.c, earmelfb_nacl.c): New targets.
+ * Makefile.in: Regenerated.
+
2012-04-11 Tristan Gingold <gingold@adacore.com>
* scripttempl/ia64vms.sc: New file.
earmelf_fbsd.c \
earmelf_linux.c \
earmelf_linux_eabi.c \
+ earmelf_nacl.c \
earmelf_nbsd.c \
earmelf_vxworks.c \
earmelfb.c \
earmelfb_linux.c \
earmelfb_linux_eabi.c \
+ earmelfb_nacl.c \
earmelfb_nbsd.c \
earmnbsd.c \
earmnto.c \
$(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} armelf_linux_eabi "$(tdir_armelf_linux_abi)"
+earmelf_nacl.c: $(srcdir)/emulparams/armelf_nacl.sh \
+ $(srcdir)/emulparams/armelf_linux_eabi.sh \
+ $(srcdir)/emulparams/armelf_linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} armelf_nacl "$(tdir_armelf_nacl)"
earmelf_nbsd.c: $(srcdir)/emulparams/armelf_nbsd.sh \
$(srcdir)/emulparams/armelf.sh \
$(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
$(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} armelfb_linux_eabi "$(tdir_armelfb_linux_abi)"
+earmelfb_nacl.c: $(srcdir)/emulparams/armelfb_nacl.sh \
+ $(srcdir)/emulparams/armelf_nacl.sh \
+ $(srcdir)/emulparams/armelf_linux_eabi.sh \
+ $(srcdir)/emulparams/armelf_linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} armelfb_nacl "$(tdir_armelfb_nacl)"
earmelfb_nbsd.c: $(srcdir)/emulparams/armelfb_nbsd.sh \
$(srcdir)/emulparams/armelf_nbsd.sh \
$(srcdir)/emulparams/armelf.sh \
earmelf_fbsd.c \
earmelf_linux.c \
earmelf_linux_eabi.c \
+ earmelf_nacl.c \
earmelf_nbsd.c \
earmelf_vxworks.c \
earmelfb.c \
earmelfb_linux.c \
earmelfb_linux_eabi.c \
+ earmelfb_nacl.c \
earmelfb_nbsd.c \
earmnbsd.c \
earmnto.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_fbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_linux.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_linux_eabi.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_nacl.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_nbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_vxworks.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_linux.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_linux_eabi.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_nacl.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_nbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmnbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmnto.Po@am__quote@
$(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} armelf_linux_eabi "$(tdir_armelf_linux_abi)"
+earmelf_nacl.c: $(srcdir)/emulparams/armelf_nacl.sh \
+ $(srcdir)/emulparams/armelf_linux_eabi.sh \
+ $(srcdir)/emulparams/armelf_linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} armelf_nacl "$(tdir_armelf_nacl)"
earmelf_nbsd.c: $(srcdir)/emulparams/armelf_nbsd.sh \
$(srcdir)/emulparams/armelf.sh \
$(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
$(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} armelfb_linux_eabi "$(tdir_armelfb_linux_abi)"
+earmelfb_nacl.c: $(srcdir)/emulparams/armelfb_nacl.sh \
+ $(srcdir)/emulparams/armelf_nacl.sh \
+ $(srcdir)/emulparams/armelf_linux_eabi.sh \
+ $(srcdir)/emulparams/armelf_linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} armelfb_nacl "$(tdir_armelfb_nacl)"
earmelfb_nbsd.c: $(srcdir)/emulparams/armelfb_nbsd.sh \
$(srcdir)/emulparams/armelf_nbsd.sh \
$(srcdir)/emulparams/armelf.sh \
targ_extra_emuls="armelf armelfb armelfb_linux"
targ_extra_libpath="armelfb_linux"
;;
+arm*b-*-nacl*) targ_emul=armelfb_nacl
+ targ_extra_emuls="armelf_nacl elf_i386_nacl"
+ targ_extra_libpath=$targ_extra_emuls
+ targ64_extra_emuls="elf32_x86_64_nacl elf_x86_64_nacl"
+ targ64_extra_libpath=$targ64_extra_emuls
+ ;;
+arm*-*-nacl*) targ_emul=armelf_nacl
+ targ_extra_emuls="armelfb_nacl elf_i386_nacl"
+ targ_extra_libpath=$targ_extra_emuls
+ targ64_extra_emuls="elf32_x86_64_nacl elf_x86_64_nacl"
+ targ64_extra_libpath=$targ64_extra_emuls
+ ;;
arm*-*-uclinux*eabi*) targ_emul=armelf_linux_eabi
targ_extra_emuls=armelfb_linux_eabi
targ_extra_libpath=$targ_extra_emuls
i[3-7]86-*-chaos) targ_emul=elf_i386_chaos
;;
i[3-7]86-*-nacl*) targ_emul=elf_i386_nacl
+ targ_extra_emuls="armelf_nacl armelfb_nacl"
+ targ_extra_libpath=$targ_extra_emuls
targ64_extra_emuls="elf32_x86_64_nacl elf_x86_64_nacl"
- targ64_extra_libpath="elf32_x86_64_nacl elf_x86_64_nacl"
+ targ64_extra_libpath=$targ64_extra_emuls
;;
x86_64-*-nacl*) targ_emul=elf32_x86_64_nacl
- targ_extra_emuls="elf_i386_nacl elf_x86_64_nacl"
- targ_extra_libpath="elf_i386_nacl elf_x86_64_nacl"
+ targ_extra_emuls="elf_i386_nacl elf_x86_64_nacl armelf_nacl armelfb_nacl"
+ targ_extra_libpath=$targ_extra_emuls
tdir_elf_i386_nacl=`echo ${targ_alias} | sed -e 's/x86_64/i386/'`
;;
i860-*-coff) targ_emul=coff_i860 ;;
--- /dev/null
+. ${srcdir}/emulparams/armelf_linux_eabi.sh
+. ${srcdir}/emulparams/elf_nacl.sh
+BIG_OUTPUT_FORMAT="elf32-bigarm-nacl"
+LITTLE_OUTPUT_FORMAT="elf32-littlearm-nacl"
+OUTPUT_FORMAT="$LITTLE_OUTPUT_FORMAT"
--- /dev/null
+. ${srcdir}/emulparams/armelf_nacl.sh
+OUTPUT_FORMAT="$BIG_OUTPUT_FORMAT"
+2012-04-12 Roland McGrath <mcgrathr@google.com>
+
+ * ld-arm/arm-elf.exp (armelftests): Split out into ...
+ (armelftests_common, armelftests_nonacl): ... these two.
+ (armeabitests): Split out into ...
+ (armeabitests_common, armeabitests_nonacl): ... these two.
+ Omit _nonacl sets for arm*-*-nacl* targets.
+
+ * ld-arm/farcall-mix.d: Don't match exact addresses, only symbolic ones.
+ * ld-arm/farcall-mix2.d: Likewise.
+ * ld-arm/farcall-group.d: Likewise.
+
+ * ld-arm/tls-gdesc-got.d: Match variant file formats too.
+ Accept some variation in exact addresses.
+
+ * ld-arm/thumb2-b-interwork.d: Match variant file formats too.
+ Fix regexps not to care about exact addresses where not relevant.
+
+ * ld-arm/thumb2-bl-undefweak.d: Match any hex strings, not any
+ strings of particular exact lengths.
+ * ld-arm/thumb2-bl-undefweak1.d: Likewise.
+
+ * ld-arm/arm-app.r: Match variant file formats too.
+ * ld-arm/arm-app-abs32.r: Likewise.
+ * ld-arm/arm-lib.d: Likewise.
+ * ld-arm/arm-lib.r: Likewise.
+ * ld-arm/arm-static-app.r: Likewise.
+ * ld-arm/armv4-bx.d: Likewise.
+ * ld-arm/data-only-map.d: Likewise.
+ * ld-arm/group-relocs.d: Likewise.
+ * ld-arm/jump19.d: Likewise.
+ * ld-arm/reloc-boundaries.d: Likewise.
+ * ld-arm/thumb1-bl.d: Likewise.
+ * ld-arm/thumb2-bl.d: Likewise.
+ * ld-arm/tls-app.d: Likewise.
+ * ld-arm/tls-app.r: Likewise.
+ * ld-arm/tls-gdierelax.d: Likewise.
+ * ld-arm/tls-gdierelax2.d: Likewise.
+ * ld-arm/tls-gdlerelax.d: Likewise.
+ * ld-arm/tls-lib.d: Likewise.
+ * ld-arm/tls-lib.r: Likewise.
+ * ld-arm/tls-mixed.r: Likewise.
+ * ld-arm/vfp11-fix-none.d: Likewise.
+ * ld-arm/vfp11-fix-scalar.d: Likewise.
+ * ld-arm/vfp11-fix-vector.d: Likewise.
+ * ld-arm/arm-static-app.d: Likewise.
+ Fix regexps not to care about exact number of leading spaces.
+ * ld-arm/arm-app-abs32.d: Likewise.
+ * ld-arm/fix-arm1176-off.d: Likewise.
+ * ld-arm/fix-arm1176-on.d: Likewise.
+
+ * ld-arm/arm-elf.exp: Treat nacl targets like eabi targets.
+
2012-04-09 Roland McGrath <mcgrathr@google.com>
* ld-elf/eh1.d: Add explicit --64 to as options, and explicit
-tmpdir/arm-app-abs32: file format elf32-(little|big)arm
+tmpdir/arm-app-abs32: file format elf32-(little|big)arm.*
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address .*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10>
- .*: e08fe00e add lr, pc, lr
- .*: e5bef008 ldr pc, \[lr, #8\]!
- .*: .* .*
- .*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; .*
- .*: e5bcf.* ldr pc, \[ip, #.*\]!.*
+ +.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+ +.*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10>
+ +.*: e08fe00e add lr, pc, lr
+ +.*: e5bef008 ldr pc, \[lr, #8\]!
+ +.*: .* .*
+ +.*: e28fc6.* add ip, pc, #.*
+ +.*: e28cca.* add ip, ip, #.* ; .*
+ +.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <_start>:
- .*: e1a0c00d mov ip, sp
- .*: e92dd800 push {fp, ip, lr, pc}
- .*: e59f0004 ldr r0, \[pc, #4\] ; .* <_start\+0x14>
- .*: e89d6800 ldm sp, {fp, sp, lr}
- .*: e12fff1e bx lr
- .*: .* .*
+ +.*: e1a0c00d mov ip, sp
+ +.*: e92dd800 push {fp, ip, lr, pc}
+ +.*: e59f0004 ldr r0, \[pc, #4\] ; .* <_start\+0x14>
+ +.*: e89d6800 ldm sp, {fp, sp, lr}
+ +.*: e12fff1e bx lr
+ +.*: .* .*
.* <app_func2>:
- .*: e12fff1e bx lr
+ +.*: e12fff1e bx lr
-tmpdir/arm-app-abs32: file format elf32-(little|big)arm
+tmpdir/arm-app-abs32: file format elf32-(little|big)arm.*
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
-tmpdir/arm-app.*: file format elf32-(little|big)arm
+tmpdir/arm-app.*: file format elf32-(little|big)arm.*
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
# Expect script for various ARM ELF tests.
-# Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+# Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2012
# Free Software Foundation, Inc.
#
# This file is part of the GNU Binutils.
# nm: Apply nm options on result. Compare with regex (last arg).
# readelf: Apply readelf options on result. Compare with regex (last arg).
-set armelftests {
+set armelftests_common {
{"Group relocations" "-Ttext 0x8000 --section-start zero=0x0 --section-start alpha=0xeef0 --section-start beta=0xffeef0" "" {group-relocs.s}
{{objdump -dr group-relocs.d}}
"group-relocs"}
{"Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x401000" "" {thumb1-bl.s}
{{objdump -dr thumb1-bl.d}}
"thumb1-bl"}
- {"Simple non-PIC shared library" "-shared" "" {arm-lib.s}
- {{objdump -fdw arm-lib.d} {objdump -Rw arm-lib.r}}
- "arm-lib.so"}
- {"Simple PIC shared library" "-shared" "" {arm-lib-plt32.s}
- {{objdump -fdw arm-lib-plt32.d} {objdump -Rw arm-lib-plt32.r}}
- "arm-lib-plt32.so"}
{"Indirect cross-library function reference (set-up)"
"-shared" "" {arm-lib-plt-2a.s}
{}
"-shared tmpdir/arm-lib-plt-2a.so" "" {arm-lib-plt-2b.s}
{{objdump -dr arm-lib-plt-2.dd} {readelf --relocs arm-lib-plt-2.rd}}
"arm-lib-plt-2b.so"}
- {"Simple dynamic application" "tmpdir/arm-lib.so" "" {arm-app.s}
- {{objdump -fdw arm-app.d} {objdump -Rw arm-app.r}}
- "arm-app"}
{"Simple static application" "" "" {arm-static-app.s}
{{objdump -fdw arm-static-app.d} {objdump -rw arm-static-app.r}}
"arm-static-app"}
- {"Non-pcrel function reference" "tmpdir/arm-lib.so" "" {arm-app-abs32.s}
- {{objdump -fdw arm-app-abs32.d} {objdump -Rw arm-app-abs32.r}}
- "arm-app-abs32"}
- {"Thumb shared library with ARM entry points" "-shared -T arm-lib.ld" "-mthumb-interwork"
- {mixed-lib.s}
- {{objdump -fdw armthumb-lib.d} {readelf -Ds armthumb-lib.sym}}
- "armthumb-lib.so"}
- {"Mixed ARM/Thumb shared library" "-shared -T arm-lib.ld -use-blx" ""
- {mixed-lib.s}
- {{objdump -fdw mixed-lib.d} {objdump -Rw mixed-lib.r}
- {readelf -Ds mixed-lib.sym}}
- "mixed-lib.so"}
- {"Mixed ARM/Thumb dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld" ""
- {mixed-app.s}
- {{objdump -fdw mixed-app.d} {objdump -Rw mixed-app.r}
- {readelf -Ds mixed-app.sym}}
- "mixed-app"}
- {"Mixed ARM/Thumb arch5 dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" ""
- {mixed-app.s}
- {{objdump -fdw mixed-app-v5.d} {objdump -Rw mixed-app.r}
- {readelf -Ds mixed-app.sym}}
- "mixed-app-v5"}
{"target1-abs" "-static --target1-abs -T arm.ld" "" {arm-target1.s}
{{objdump -s arm-target1-abs.d}}
"arm-target1-abs"}
{"TLS gnu shared library got" "-shared -T arm-dyn.ld" "" {tls-gdesc-got.s}
{{objdump "-fDR -j .got" tls-gdesc-got.d}}
"tls-lib2-got.so"}
- {"TLS gnu shared library inlined trampoline" "--no-fix-arm1176 -shared -T arm-dyn.ld" "" {tls-descseq.s}
- {{objdump -fdw tls-descseq.d} {objdump -Rw tls-descseq.r}}
- "tls-lib2inline.so"}
- {"TLS shared library gdesc local" "--no-fix-arm1176 -shared -T arm-dyn.ld" "" {tls-lib-loc.s}
- {{objdump -fdw tls-lib-loc.d} {objdump -Rw tls-lib-loc.r}}
- "tls-lib-loc.so"}
{"TLS gnu GD to IE relaxation" "-static -T arm-dyn.ld" "" {tls-gdierelax.s}
{{objdump -fdw tls-gdierelax.d}}
"tls-app-rel-ie"}
"-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-b.s}
{{objdump -dr cortex-a8-fix-b.d}}
"cortex-a8-fix-b"}
- {"Cortex-A8 erratum fix, b.w to PLT"
- "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL"
- {cortex-a8-fix-b-plt.s}
- {{objdump -dr cortex-a8-fix-b-plt.d}}
- "cortex-a8-fix-b-plt"}
{"Cortex-A8 erratum fix, bl.w"
"-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-bl.s}
{{objdump -dr cortex-a8-fix-bl.d}}
"cortex-a8-fix-bl"}
- {"Cortex-A8 erratum fix, bl.w to PLT"
- "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL"
- {cortex-a8-fix-bl-plt.s}
- {{objdump -dr cortex-a8-fix-bl-plt.d}}
- "cortex-a8-fix-bl-plt"}
{"Cortex-A8 erratum fix, bcc.w"
"-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-bcc.s}
{{objdump -dr cortex-a8-fix-bcc.d}}
"cortex-a8-fix-bcc"}
- {"Cortex-A8 erratum fix, bcc.w to PLT"
- "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL"
- {cortex-a8-fix-bcc-plt.s}
- {{objdump -dr cortex-a8-fix-bcc-plt.d}}
- "cortex-a8-fix-bcc-plt"}
{"Cortex-A8 erratum fix, blx.w"
"-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-blx.s}
{{objdump -dr cortex-a8-fix-blx.d}}
"cortex-a8-fix-blx"}
- {"Cortex-A8 erratum fix, blx.w to PLT"
- "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL"
- {cortex-a8-fix-blx-plt.s}
- {{objdump -dr cortex-a8-fix-blx-plt.d}}
- "cortex-a8-fix-blx-plt"}
{"Cortex-A8 erratum fix, relocate b.w to ARM"
"-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-b-rel.s}
{{objdump -dr cortex-a8-fix-b-rel-arm.d}}
"-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bl-rel.s}
{{objdump -dr cortex-a8-fix-bl-rel-thumb.d}}
"cortex-a8-fix-bl-rel-thumb"}
- {"Cortex-A8 erratum fix, relocate bl.w to PLT"
- "-EL --section-start=.plt=0x8e00 -Ttext=0x8f00 --fix-cortex-a8 -shared"
- "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bl-rel.s}
- {{objdump -dr cortex-a8-fix-bl-rel-plt.d}}
- "cortex-a8-fix-bl-rel-thumb"}
{"Cortex-A8 erratum fix, relocate b<cond>.w to Thumb"
"-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bcc-rel.s}
{{objdump -dr cortex-a8-fix-bcc-rel-thumb.d}}
"" {exec-got-1b.s}
{{readelf --relocs exec-got-1.d}}
"exec-got-1"}
+ {"abs call" "-T arm.ld" "" {abs-call-1.s}
+ {{objdump -d abs-call-1.d}}
+ "abs-call-1"}
+}
+
+set armelftests_nonacl {
+ {"Simple non-PIC shared library" "-shared" "" {arm-lib.s}
+ {{objdump -fdw arm-lib.d} {objdump -Rw arm-lib.r}}
+ "arm-lib.so"}
+ {"Simple PIC shared library" "-shared" "" {arm-lib-plt32.s}
+ {{objdump -fdw arm-lib-plt32.d} {objdump -Rw arm-lib-plt32.r}}
+ "arm-lib-plt32.so"}
+ {"Simple dynamic application" "tmpdir/arm-lib.so" "" {arm-app.s}
+ {{objdump -fdw arm-app.d} {objdump -Rw arm-app.r}}
+ "arm-app"}
+ {"Non-pcrel function reference" "tmpdir/arm-lib.so" "" {arm-app-abs32.s}
+ {{objdump -fdw arm-app-abs32.d} {objdump -Rw arm-app-abs32.r}}
+ "arm-app-abs32"}
+ {"Thumb shared library with ARM entry points" "-shared -T arm-lib.ld" "-mthumb-interwork"
+ {mixed-lib.s}
+ {{objdump -fdw armthumb-lib.d} {readelf -Ds armthumb-lib.sym}}
+ "armthumb-lib.so"}
+ {"Mixed ARM/Thumb shared library" "-shared -T arm-lib.ld -use-blx" ""
+ {mixed-lib.s}
+ {{objdump -fdw mixed-lib.d} {objdump -Rw mixed-lib.r}
+ {readelf -Ds mixed-lib.sym}}
+ "mixed-lib.so"}
+ {"Mixed ARM/Thumb dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld" ""
+ {mixed-app.s}
+ {{objdump -fdw mixed-app.d} {objdump -Rw mixed-app.r}
+ {readelf -Ds mixed-app.sym}}
+ "mixed-app"}
+ {"Mixed ARM/Thumb arch5 dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" ""
+ {mixed-app.s}
+ {{objdump -fdw mixed-app-v5.d} {objdump -Rw mixed-app.r}
+ {readelf -Ds mixed-app.sym}}
+ "mixed-app-v5"}
+ {"TLS gnu shared library inlined trampoline" "--no-fix-arm1176 -shared -T arm-dyn.ld" "" {tls-descseq.s}
+ {{objdump -fdw tls-descseq.d} {objdump -Rw tls-descseq.r}}
+ "tls-lib2inline.so"}
+ {"TLS shared library gdesc local" "--no-fix-arm1176 -shared -T arm-dyn.ld" "" {tls-lib-loc.s}
+ {{objdump -fdw tls-lib-loc.d} {objdump -Rw tls-lib-loc.r}}
+ "tls-lib-loc.so"}
+ {"Cortex-A8 erratum fix, b.w to PLT"
+ "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL"
+ {cortex-a8-fix-b-plt.s}
+ {{objdump -dr cortex-a8-fix-b-plt.d}}
+ "cortex-a8-fix-b-plt"}
+ {"Cortex-A8 erratum fix, bl.w to PLT"
+ "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL"
+ {cortex-a8-fix-bl-plt.s}
+ {{objdump -dr cortex-a8-fix-bl-plt.d}}
+ "cortex-a8-fix-bl-plt"}
+ {"Cortex-A8 erratum fix, bcc.w to PLT"
+ "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL"
+ {cortex-a8-fix-bcc-plt.s}
+ {{objdump -dr cortex-a8-fix-bcc-plt.d}}
+ "cortex-a8-fix-bcc-plt"}
+ {"Cortex-A8 erratum fix, blx.w to PLT"
+ "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL"
+ {cortex-a8-fix-blx-plt.s}
+ {{objdump -dr cortex-a8-fix-blx-plt.d}}
+ "cortex-a8-fix-blx-plt"}
+ {"Cortex-A8 erratum fix, relocate bl.w to PLT"
+ "-EL --section-start=.plt=0x8e00 -Ttext=0x8f00 --fix-cortex-a8 -shared"
+ "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bl-rel.s}
+ {{objdump -dr cortex-a8-fix-bl-rel-plt.d}}
+ "cortex-a8-fix-bl-rel-thumb"}
{"IFUNC test 1" "-T ifunc-static.ld" "" {ifunc-1.s}
{{objdump -d ifunc-1.dd}
{objdump {-s -j.data -j.got} ifunc-1.gd}
{objdump {-s -j.data -j.got} ifunc-16.gd}
{readelf -r ifunc-16.rd}}
"ifunc-16"}
- {"abs call" "-T arm.ld" "" {abs-call-1.s}
- {{objdump -d abs-call-1.d}}
- "abs-call-1"}
}
-run_ld_link_tests $armelftests
+run_ld_link_tests $armelftests_common
+if { ![istarget "arm*-*-nacl*"] } {
+ run_ld_link_tests $armelftests_nonacl
+}
+
run_dump_test "group-relocs-alu-bad"
run_dump_test "group-relocs-ldr-bad"
run_dump_test "group-relocs-ldrs-bad"
# Exclude non-ARM-EABI targets.
-if { ![istarget "arm*-*-*eabi"] } {
+if { ![istarget "arm*-*-*eabi"] && ![istarget "arm*-*-nacl*"] } {
# Special variants of these tests, as a different farcall stub is
# generated for a non-ARM-EABI target: indeed in such a case,
# there are no attributes to indicate that blx can be used.
}
# Farcalls stubs are fully supported for ARM-EABI only
-set armeabitests {
+set armeabitests_common {
{"EABI attribute merging" "-r" "" {attr-merge.s attr-merge.s}
{{readelf -A attr-merge.attr}}
"attr-merge"}
{{objdump -d farcall-arm-arm.d}}
"farcall-arm-arm-be"}
+ {"Multiple farcalls" "-Ttext 0x1000 --section-start .foo=0x2002020" "" {farcall-mix.s}
+ {{objdump -d farcall-mix.d}}
+ "farcall-mix"}
+ {"Multiple farcalls from several sections" "-Ttext 0x1000 --section-start .mytext=0x2000 --section-start .foo=0x2003020" "" {farcall-mix2.s}
+ {{objdump -d farcall-mix2.d}}
+ "farcall-mix2"}
+
+ {"Default group size" "-Ttext 0x1000 --section-start .foo=0x2003020" "" {farcall-group.s farcall-group2.s}
+ {{objdump -d farcall-group.d}}
+ "farcall-group-default"}
+ {"Group size=2" "-Ttext 0x1000 --section-start .foo=0x2003020 --stub-group-size=2" "" {farcall-group.s farcall-group2.s}
+ {{objdump -d farcall-group-size2.d}}
+ "farcall-group-size2"}
+ {"Group size limit" "-Ttext 0x1000 --section-start .far=0x2003020" "" {farcall-group3.s farcall-group4.s}
+ {{objdump -d farcall-group-limit.d}}
+ "farcall-group-limit"}
+
+ {"Long branch with mixed text and data" "-T arm.ld" "" {farcall-data.s}
+ {{objdump -dr farcall-data.d}}
+ "farcall-data"}
+
+ {"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
+ "--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000"
+ "-march=armv7-a -mthumb"
+ {jump-reloc-veneers.s}
+ {{objdump -d jump-reloc-veneers-short1.d}}
+ "jump-reloc-veneers-short1"}
+ {"R_ARM_THM_JUMP24 Relocation veneers: Short 2"
+ "--no-fix-arm1176 --section-start destsect=0x00900000 --section-start .text=0x8000"
+ "-march=armv7-a -mthumb"
+ {jump-reloc-veneers.s}
+ {{objdump -d jump-reloc-veneers-short2.d}}
+ "jump-reloc-veneers-short2"}
+ {"R_ARM_THM_JUMP24 Relocation veneers: Long"
+ "--no-fix-arm1176 --section-start destsect=0x09000000 --section-start .text=0x8000"
+ "-march=armv7-a -mthumb"
+ {jump-reloc-veneers.s}
+ {{objdump -d jump-reloc-veneers-long.d}}
+ "jump-reloc-veneers-long"}
+
+ {"erratum 760522 fix (default for v6z)" "--section-start=.foo=0x2001014"
+ "-march=armv6z" {fix-arm1176.s}
+ {{objdump -d fix-arm1176-on.d}}
+ "fix-arm1176-1"}
+ {"erratum 760522 fix (explicitly on at v6z)" "--section-start=.foo=0x2001014 --fix-arm1176"
+ "-march=armv6z" {fix-arm1176.s}
+ {{objdump -d fix-arm1176-on.d}}
+ "fix-arm1176-2"}
+ {"erratum 760522 fix (explicitly off at v6z)" "--section-start=.foo=0x2001014 --no-fix-arm1176"
+ "-march=armv6z" {fix-arm1176.s}
+ {{objdump -d fix-arm1176-off.d}}
+ "fix-arm1176-3"}
+ {"erratum 760522 fix (default for v5)" "--section-start=.foo=0x2001014 "
+ "-march=armv5te" {fix-arm1176.s}
+ {{objdump -d fix-arm1176-on.d}}
+ "fix-arm1176-4"}
+ {"erratum 760522 fix (default for v7-a)" "--section-start=.foo=0x2001014 "
+ "-march=armv7-a" {fix-arm1176.s}
+ {{objdump -d fix-arm1176-off.d}}
+ "fix-arm1176-5"}
+ {"erratum 760522 fix (default for ARM1156)" "--section-start=.foo=0x2001014 "
+ "-mcpu=arm1156t2f-s" {fix-arm1176.s}
+ {{objdump -d fix-arm1176-off.d}}
+ "fix-arm1176-6"}
+}
+
+set armeabitests_nonacl {
{"ARM-Thumb farcall" "-Ttext 0x1000 --section-start .foo=0x2001014" "" {farcall-arm-thumb.s}
{{objdump -d farcall-arm-thumb.d}}
"farcall-arm-thumb"}
{{objdump -d farcall-thumb-arm-pic-veneer.d}}
"farcall-thumb-arm-pic-veneer"}
- {"Multiple farcalls" "-Ttext 0x1000 --section-start .foo=0x2002020" "" {farcall-mix.s}
- {{objdump -d farcall-mix.d}}
- "farcall-mix"}
- {"Multiple farcalls from several sections" "-Ttext 0x1000 --section-start .mytext=0x2000 --section-start .foo=0x2003020" "" {farcall-mix2.s}
- {{objdump -d farcall-mix2.d}}
- "farcall-mix2"}
-
- {"Default group size" "-Ttext 0x1000 --section-start .foo=0x2003020" "" {farcall-group.s farcall-group2.s}
- {{objdump -d farcall-group.d}}
- "farcall-group-default"}
- {"Group size=2" "-Ttext 0x1000 --section-start .foo=0x2003020 --stub-group-size=2" "" {farcall-group.s farcall-group2.s}
- {{objdump -d farcall-group-size2.d}}
- "farcall-group-size2"}
- {"Group size limit" "-Ttext 0x1000 --section-start .far=0x2003020" "" {farcall-group3.s farcall-group4.s}
- {{objdump -d farcall-group-limit.d}}
- "farcall-group-limit"}
-
{"Mixed ARM/Thumb dynamic application with farcalls" "tmpdir/mixed-lib.so -T arm-dyn.ld --section-start .far_arm=0x2100000 --section-start .far_thumb=0x2200000" ""
{farcall-mixed-app.s}
{{objdump -fdw farcall-mixed-app.d} {objdump -Rw farcall-mixed-app.r}
{{objdump -fdw farcall-mixed-lib.d}}
"farcall-mixed-lib.so"}
- {"Long branch with mixed text and data" "-T arm.ld" "" {farcall-data.s}
- {{objdump -dr farcall-data.d}}
- "farcall-data"}
-
- {"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
- "--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000"
- "-march=armv7-a -mthumb"
- {jump-reloc-veneers.s}
- {{objdump -d jump-reloc-veneers-short1.d}}
- "jump-reloc-veneers-short1"}
- {"R_ARM_THM_JUMP24 Relocation veneers: Short 2"
- "--no-fix-arm1176 --section-start destsect=0x00900000 --section-start .text=0x8000"
- "-march=armv7-a -mthumb"
- {jump-reloc-veneers.s}
- {{objdump -d jump-reloc-veneers-short2.d}}
- "jump-reloc-veneers-short2"}
- {"R_ARM_THM_JUMP24 Relocation veneers: Long"
- "--no-fix-arm1176 --section-start destsect=0x09000000 --section-start .text=0x8000"
- "-march=armv7-a -mthumb"
- {jump-reloc-veneers.s}
- {{objdump -d jump-reloc-veneers-long.d}}
- "jump-reloc-veneers-long"}
{"TLS gnu shared library" "--no-fix-arm1176 -shared -T arm-dyn.ld" "" {tls-gdesc.s}
{{objdump -fdw tls-gdesc.d} {objdump -Rw tls-gdesc.r}}
"tls-lib2.so"}
{"TLS thumb1" "-shared -T arm-dyn.ld --section-start .foo=0x4001000" "" {tls-thumb1.s}
{{objdump -fdw tls-thumb1.d}}
"tls-thumb1"}
+}
- {"erratum 760522 fix (default for v6z)" "--section-start=.foo=0x2001014"
- "-march=armv6z" {fix-arm1176.s}
- {{objdump -d fix-arm1176-on.d}}
- "fix-arm1176-1"}
- {"erratum 760522 fix (explicitly on at v6z)" "--section-start=.foo=0x2001014 --fix-arm1176"
- "-march=armv6z" {fix-arm1176.s}
- {{objdump -d fix-arm1176-on.d}}
- "fix-arm1176-2"}
- {"erratum 760522 fix (explicitly off at v6z)" "--section-start=.foo=0x2001014 --no-fix-arm1176"
- "-march=armv6z" {fix-arm1176.s}
- {{objdump -d fix-arm1176-off.d}}
- "fix-arm1176-3"}
- {"erratum 760522 fix (default for v5)" "--section-start=.foo=0x2001014 "
- "-march=armv5te" {fix-arm1176.s}
- {{objdump -d fix-arm1176-on.d}}
- "fix-arm1176-4"}
- {"erratum 760522 fix (default for v7-a)" "--section-start=.foo=0x2001014 "
- "-march=armv7-a" {fix-arm1176.s}
- {{objdump -d fix-arm1176-off.d}}
- "fix-arm1176-5"}
- {"erratum 760522 fix (default for ARM1156)" "--section-start=.foo=0x2001014 "
- "-mcpu=arm1156t2f-s" {fix-arm1176.s}
- {{objdump -d fix-arm1176-off.d}}
- "fix-arm1176-6"}
+run_ld_link_tests $armeabitests_common
+if { ![istarget "arm*-*-nacl*"] } {
+ run_ld_link_tests $armeabitests_nonacl
}
-run_ld_link_tests $armeabitests
run_dump_test "attr-merge-div-00"
run_dump_test "attr-merge-div-01"
run_dump_test "attr-merge-div-10"
-tmpdir/arm-lib.so: file format elf32-(little|big)arm
+tmpdir/arm-lib.so: file format elf32-(little|big)arm.*
architecture: arm, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
-tmpdir/arm-lib.so: file format elf32-(little|big)arm
+tmpdir/arm-lib.so: file format elf32-(little|big)arm.*
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
-tmpdir/arm-static-app: file format elf32-(little|big)arm
+tmpdir/arm-static-app: file format elf32-(little|big)arm.*
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x.*
Disassembly of section .text:
.* <_start>:
- .*: e1a0c00d mov ip, sp
- .*: e92dd800 push {fp, ip, lr, pc}
- .*: eb000001 bl .* <app_func>
- .*: e89d6800 ldm sp, {fp, sp, lr}
- .*: e12fff1e bx lr
+ +.*: e1a0c00d mov ip, sp
+ +.*: e92dd800 push {fp, ip, lr, pc}
+ +.*: eb000001 bl .* <app_func>
+ +.*: e89d6800 ldm sp, {fp, sp, lr}
+ +.*: e12fff1e bx lr
.* <app_func>:
- .*: e1a0c00d mov ip, sp
- .*: e92dd800 push {fp, ip, lr, pc}
- .*: eb000001 bl .* <app_func2>
- .*: e89d6800 ldm sp, {fp, sp, lr}
- .*: e12fff1e bx lr
+ +.*: e1a0c00d mov ip, sp
+ +.*: e92dd800 push {fp, ip, lr, pc}
+ +.*: eb000001 bl .* <app_func2>
+ +.*: e89d6800 ldm sp, {fp, sp, lr}
+ +.*: e12fff1e bx lr
.* <app_func2>:
- .*: e12fff1e bx lr
+ +.*: e12fff1e bx lr
-tmpdir/arm-static-app: file format elf32-(little|big)arm
+tmpdir/arm-static-app: file format elf32-(little|big)arm.*
-.*: .*file format elf32-(big|little)arm
+.*: .*file format elf32-(big|little)arm.*
Disassembly of section \.text:
-[^:]*: file format elf32-littlearm
+[^:]*: file format elf32-littlearm.*
Disassembly of section \.text:
Disassembly of section .text:
-00001000 <_start>:
- 1000: eb00000c bl 1038 <__bar_from_arm>
- 1004: eb00000e bl 1044 <__bar2_veneer>
-
-00001008 <myfunc>:
- 1008: eb000008 bl 1030 <__bar3_veneer>
- 100c: eb000004 bl 1024 <__bar4_from_arm>
- 1010: eb000000 bl 1018 <__bar5_from_arm>
- 1014: 00000000 andeq r0, r0, r0
-
-00001018 <__bar5_from_arm>:
- 1018: e59fc000 ldr ip, \[pc\] ; 1020 <__bar5_from_arm\+0x8>
- 101c: e12fff1c bx ip
- 1020: 0200302f .word 0x0200302f
-
-00001024 <__bar4_from_arm>:
- 1024: e59fc000 ldr ip, \[pc\] ; 102c <__bar4_from_arm\+0x8>
- 1028: e12fff1c bx ip
- 102c: 0200302d .word 0x0200302d
-
-00001030 <__bar3_veneer>:
- 1030: e51ff004 ldr pc, \[pc, #-4\] ; 1034 <__bar3_veneer\+0x4>
- 1034: 02003028 .word 0x02003028
-
-00001038 <__bar_from_arm>:
- 1038: e59fc000 ldr ip, \[pc\] ; 1040 <__bar_from_arm\+0x8>
- 103c: e12fff1c bx ip
- 1040: 02003021 .word 0x02003021
-
-00001044 <__bar2_veneer>:
- 1044: e51ff004 ldr pc, \[pc, #-4\] ; 1048 <__bar2_veneer\+0x4>
- 1048: 02003024 .word 0x02003024
+[0-9a-f]+ <_start>:
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar_from_arm>
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar2_veneer>
+
+[0-9a-f]+ <myfunc>:
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar3_veneer>
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar4_from_arm>
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar5_from_arm>
+ +[0-9a-f]+: 00000000 andeq r0, r0, r0
+
+[0-9a-f]+ <__bar5_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 0200302f .word 0x0200302f
+
+[0-9a-f]+ <__bar4_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 0200302d .word 0x0200302d
+
+[0-9a-f]+ <__bar3_veneer>:
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: 02003028 .word 0x02003028
+
+[0-9a-f]+ <__bar_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 02003021 .word 0x02003021
+
+[0-9a-f]+ <__bar2_veneer>:
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: 02003024 .word 0x02003024
...
Disassembly of section .foo:
-02003020 <bar>:
- 2003020: 4770 bx lr
+[0-9a-f]+ <bar>:
+ +[0-9a-f]+: 4770 bx lr
...
-02003024 <bar2>:
- 2003024: e12fff1e bx lr
+[0-9a-f]+ <bar2>:
+ +[0-9a-f]+: e12fff1e bx lr
-02003028 <bar3>:
- 2003028: e12fff1e bx lr
+[0-9a-f]+ <bar3>:
+ +[0-9a-f]+: e12fff1e bx lr
-0200302c <bar4>:
- 200302c: 4770 bx lr
+[0-9a-f]+ <bar4>:
+ +[0-9a-f]+: 4770 bx lr
-0200302e <bar5>:
- 200302e: 4770 bx lr
+[0-9a-f]+ <bar5>:
+ +[0-9a-f]+: 4770 bx lr
Disassembly of section .text:
-00001000 <_start>:
- 1000: eb000004 bl 1018 <__bar_from_arm>
- 1004: eb00000e bl 1044 <__bar2_veneer>
- 1008: eb000005 bl 1024 <__bar3_veneer>
- 100c: eb000009 bl 1038 <__bar4_from_arm>
- 1010: eb000005 bl 102c <__bar5_from_arm>
- 1014: 00000000 andeq r0, r0, r0
-
-00001018 <__bar_from_arm>:
- 1018: e59fc000 ldr ip, \[pc\] ; 1020 <__bar_from_arm\+0x8>
- 101c: e12fff1c bx ip
- 1020: 02002021 .word 0x02002021
-00001024 <__bar3_veneer>:
- 1024: e51ff004 ldr pc, \[pc, #-4\] ; 1028 <__bar3_veneer\+0x4>
- 1028: 02002028 .word 0x02002028
-0000102c <__bar5_from_arm>:
- 102c: e59fc000 ldr ip, \[pc\] ; 1034 <__bar5_from_arm\+0x8>
- 1030: e12fff1c bx ip
- 1034: 0200202f .word 0x0200202f
-00001038 <__bar4_from_arm>:
- 1038: e59fc000 ldr ip, \[pc\] ; 1040 <__bar4_from_arm\+0x8>
- 103c: e12fff1c bx ip
- 1040: 0200202d .word 0x0200202d
-
-00001044 <__bar2_veneer>:
- 1044: e51ff004 ldr pc, \[pc, #-4\] ; 1048 <__bar2_veneer\+0x4>
- 1048: 02002024 .word 0x02002024
+[0-9a-f]+ <_start>:
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar_from_arm>
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar2_veneer>
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar3_veneer>
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar4_from_arm>
+ +[0-9a-f]+: [0-9a-f]{8} bl [0-9a-f]+ <__bar5_from_arm>
+ +[0-9a-f]+: 00000000 andeq r0, r0, r0
+
+[0-9a-f]+ <__bar_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 02002021 .word 0x02002021
+[0-9a-f]+ <__bar3_veneer>:
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: 02002028 .word 0x02002028
+[0-9a-f]+ <__bar5_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 0200202f .word 0x0200202f
+[0-9a-f]+ <__bar4_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 0200202d .word 0x0200202d
+
+[0-9a-f]+ <__bar2_veneer>:
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: 02002024 .word 0x02002024
...
Disassembly of section .foo:
-02002020 <bar>:
- 2002020: 4770 bx lr
+[0-9a-f]+ <bar>:
+ +[0-9a-f]+: 4770 bx lr
...
-02002024 <bar2>:
- 2002024: e12fff1e bx lr
+[0-9a-f]+ <bar2>:
+ +[0-9a-f]+: e12fff1e bx lr
-02002028 <bar3>:
- 2002028: e12fff1e bx lr
+[0-9a-f]+ <bar3>:
+ +[0-9a-f]+: e12fff1e bx lr
-0200202c <bar4>:
- 200202c: 4770 bx lr
+[0-9a-f]+ <bar4>:
+ +[0-9a-f]+: 4770 bx lr
-0200202e <bar5>:
- 200202e: 4770 bx lr
+[0-9a-f]+ <bar5>:
+ +[0-9a-f]+: 4770 bx lr
Disassembly of section .text:
-00001000 <_start>:
- 1000: eb000000 bl 1008 <__bar_from_arm>
- 1004: eb000002 bl 1014 <__bar2_veneer>
-
-00001008 <__bar_from_arm>:
- 1008: e59fc000 ldr ip, \[pc\] ; 1010 <__bar_from_arm\+0x8>
- 100c: e12fff1c bx ip
- 1010: 02003021 .word 0x02003021
-00001014 <__bar2_veneer>:
- 1014: e51ff004 ldr pc, \[pc, #-4\] ; 1018 <__bar2_veneer\+0x4>
- 1018: 02003024 .word 0x02003024
- 101c: 00000000 .word 0x00000000
+[0-9a-f]+ <_start>:
+ +[0-9a-f]+: eb000000 bl [0-9a-f]+ <__bar_from_arm>
+ +[0-9a-f]+: eb000002 bl [0-9a-f]+ <__bar2_veneer>
+
+[0-9a-f]+ <__bar_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 02003021 .word 0x02003021
+[0-9a-f]+ <__bar2_veneer>:
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: 02003024 .word 0x02003024
+ +[0-9a-f]+: 00000000 .word 0x00000000
Disassembly of section .mytext:
-00002000 <__bar3_veneer-0x10>:
- 2000: eb000002 bl 2010 <__bar3_veneer>
- 2004: eb000003 bl 2018 <__bar4_from_arm>
- 2008: eb000005 bl 2024 <__bar5_from_arm>
- 200c: 00000000 andeq r0, r0, r0
-
-00002010 <__bar3_veneer>:
- 2010: e51ff004 ldr pc, \[pc, #-4\] ; 2014 <__bar3_veneer\+0x4>
- 2014: 02003028 .word 0x02003028
-
-00002018 <__bar4_from_arm>:
- 2018: e59fc000 ldr ip, \[pc\] ; 2020 <__bar4_from_arm\+0x8>
- 201c: e12fff1c bx ip
- 2020: 0200302d .word 0x0200302d
-
-00002024 <__bar5_from_arm>:
- 2024: e59fc000 ldr ip, \[pc\] ; 202c <__bar5_from_arm\+0x8>
- 2028: e12fff1c bx ip
- 202c: 0200302f .word 0x0200302f
+[0-9a-f]+ <__bar3_veneer-0x10>:
+ +[0-9a-f]+: eb000002 bl [0-9a-f]+ <__bar3_veneer>
+ +[0-9a-f]+: eb000003 bl [0-9a-f]+ <__bar4_from_arm>
+ +[0-9a-f]+: eb000005 bl [0-9a-f]+ <__bar5_from_arm>
+ +[0-9a-f]+: 00000000 andeq r0, r0, r0
+
+[0-9a-f]+ <__bar3_veneer>:
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: 02003028 .word 0x02003028
+
+[0-9a-f]+ <__bar4_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 0200302d .word 0x0200302d
+
+[0-9a-f]+ <__bar5_from_arm>:
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e12fff1c bx ip
+ +[0-9a-f]+: 0200302f .word 0x0200302f
...
Disassembly of section .foo:
-02003020 <bar>:
- 2003020: 4770 bx lr
+[0-9a-f]+ <bar>:
+ +[0-9a-f]+: 4770 bx lr
...
-02003024 <bar2>:
- 2003024: e12fff1e bx lr
+[0-9a-f]+ <bar2>:
+ +[0-9a-f]+: e12fff1e bx lr
-02003028 <bar3>:
- 2003028: e12fff1e bx lr
+[0-9a-f]+ <bar3>:
+ +[0-9a-f]+: e12fff1e bx lr
-0200302c <bar4>:
- 200302c: 4770 bx lr
+[0-9a-f]+ <bar4>:
+ +[0-9a-f]+: 4770 bx lr
-0200302e <bar5>:
- 200302e: 4770 bx lr
+[0-9a-f]+ <bar5>:
+ +[0-9a-f]+: 4770 bx lr
-.*: file format elf32-littlearm
+.*: file format elf32-littlearm.*
Disassembly of section .foo:
[0-9a-f]+ <_start>:
- [0-9a-f]+: f000 e800 blx 2001018 <__func_to_branch_to_veneer>
+ +[0-9a-f]+: f000 e800 blx 2001018 <__func_to_branch_to_veneer>
[0-9a-f]+ <__func_to_branch_to_veneer>:
- [0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; 200101c <__func_to_branch_to_veneer\+0x4>
- [0-9a-f]+: ........ .word 0x........
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; 200101c <__func_to_branch_to_veneer\+0x4>
+ +[0-9a-f]+: ........ .word 0x........
Disassembly of section .text:
[0-9a-f]+ <func_to_branch_to>:
- [0-9a-f]+: e12fff1e bx lr
+ +[0-9a-f]+: e12fff1e bx lr
-.+: file format elf32-littlearm
+.+: file format elf32-littlearm.*
Disassembly of section .foo:
[0-9a-f]+ <_start>:
- [0-9a-f]+: f000 f800 bl 2001018 <__func_to_branch_to_veneer>
+ +[0-9a-f]+: f000 f800 bl 2001018 <__func_to_branch_to_veneer>
[0-9a-f]+ <__func_to_branch_to_veneer>:
- [0-9a-f]+: 4778 bx pc
- [0-9a-f]+: 46c0 nop ; \(mov r8, r8\)
- [0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; 2001020 <__func_to_branch_to_veneer\+0x8>
- [0-9a-f]+: ........ .word 0x........
- [0-9a-f]+: 00000000 .word 0x00000000
+ +[0-9a-f]+: 4778 bx pc
+ +[0-9a-f]+: 46c0 nop ; \(mov r8, r8\)
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; 2001020 <__func_to_branch_to_veneer\+0x8>
+ +[0-9a-f]+: ........ .word 0x........
+ +[0-9a-f]+: 00000000 .word 0x00000000
Disassembly of section .text:
[0-9a-f]+ <func_to_branch_to>:
- [0-9a-f]+: e12fff1e bx lr
+ +[0-9a-f]+: e12fff1e bx lr
-tmpdir/group-relocs: file format elf32-(little|big)arm
+tmpdir/group-relocs: file format elf32-(little|big)arm.*
Disassembly of section .text:
-.*jump19: file format elf32-(big|little)arm
+.*jump19: file format elf32-(big|little)arm.*
Disassembly of section .text:
-[^:]*: file format elf32-(little|big)arm
+[^:]*: file format elf32-(little|big)arm.*
Contents of section .text:
- 80.. 80ff0080 ffff ......
+ [0-9a-f]+ 80ff0080 ffff ......
#...
-.*thumb1-bl: file format elf32-.*arm
+.*thumb1-bl: file format elf32-.*arm.*
Disassembly of section .text:
-.*thumb2-b-interwork: file format elf32-.*arm
+.*thumb2-b-interwork: file format elf32-.*arm.*
Disassembly of section .text:
-00008000 <_start>:
- 8000: f000 b802 b.w 8008 <__bar_from_thumb>
+[0-9a-f]+ <_start>:
+ +[0-9a-f]+: f000 b802 b.w [0-9a-f]+ <__bar_from_thumb>
-00008004 <bar>:
- 8004: e12fff1e bx lr
+[0-9a-f]+ <bar>:
+ +[0-9a-f]+: e12fff1e bx lr
-00008008 <__bar_from_thumb>:
- 8008: 4778 bx pc
- 800a: 46c0 nop ; \(mov r8, r8\)
- 800c: eafffffc b 8004 <bar>
+[0-9a-f]+ <__bar_from_thumb>:
+ +[0-9a-f]+: 4778 bx pc
+ +[0-9a-f]+: 46c0 nop ; \(mov r8, r8\)
+ +[0-9a-f]+: eafffffc b [0-9a-f]+ <bar>
Disassembly of section .text:
.* <foo>:
- .*: .... .... bl. ... <foo-0x.*>
+ +[0-9a-f]+: .... .... bl. [0-9a-f]+ <foo-0x[0-9a-f]+>
Disassembly of section .text:
.* <foo>:
- .*: ........ bl ... <foo-0x.*>
+ +[0-9a-f]+: ........ bl [0-9a-f]+ <foo-0x[0-9a-f]+>
-.*thumb2-bl: file format elf32-.*arm
+.*thumb2-bl: file format elf32-.*arm.*
Disassembly of section .text:
-.*: file format elf32-.*arm
+.*: file format elf32-.*arm.*
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x000081c8
-.*: file format elf32-.*arm
+.*: file format elf32-.*arm.*
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
-.*/tls-lib2-got.so: file format elf32-.*arm
+.*/tls-lib2-got.so: file format elf32-.*arm.*
architecture: arm, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
-start address 0x00008210
+start address 0x000082.0
Disassembly of section .got:
-00010310 <.*>:
- 10310: 00010288 .*
+000103.0 <.*>:
+ 103.0: 000102.8 .*
...
- 1031c: 00000008 .*
- 1031c: R_ARM_TLS_DESC \*ABS\*
- 10320: 00000000 .*
- 10324: 0000000c .*
- 10324: R_ARM_TLS_DESC \*ABS\*
- 10328: 00000000 .*
- 1032c: 80000004 .*
- 1032c: R_ARM_TLS_DESC glob1
- 10330: 00000000 .*
- 10334: 80000006 .*
- 10334: R_ARM_TLS_DESC ext2
- 10338: 00000000 .*
- 1033c: 80000007 .*
- 1033c: R_ARM_TLS_DESC ext1
- 10340: 00000000 .*
- 10344: 80000009 .*
- 10344: R_ARM_TLS_DESC glob2
+ 103.c: 00000008 .*
+ 103.c: R_ARM_TLS_DESC \*ABS\*
+ 103.0: 00000000 .*
+ 103.4: 0000000c .*
+ 103.4: R_ARM_TLS_DESC \*ABS\*
+ 103.8: 00000000 .*
+ 103.c: 80000004 .*
+ 103.c: R_ARM_TLS_DESC glob1
+ 103.0: 00000000 .*
+ 103.4: 80000006 .*
+ 103.4: R_ARM_TLS_DESC ext2
+ 103.8: 00000000 .*
+ 103.c: 80000007 .*
+ 103.c: R_ARM_TLS_DESC ext1
+ 103.0: 00000000 .*
+ 103.4: 80000009 .*
+ 103.4: R_ARM_TLS_DESC glob2
...
-tmpdir/tls-app-rel-ie: file format elf32-.*arm
+tmpdir/tls-app-rel-ie: file format elf32-.*arm.*
architecture: arm, flags 0x[0-9a-f]+:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x[0-9a-f]+
-tmpdir/tls-app-rel-ie2: file format elf32-.*arm
+tmpdir/tls-app-rel-ie2: file format elf32-.*arm.*
architecture: arm, flags 0x[0-9a-f]+:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x[0-9a-f]+
-tmpdir/tls-app-rel-le: file format elf32-.*arm
+tmpdir/tls-app-rel-le: file format elf32-.*arm.*
architecture: arm, flags 0x[0-9a-f]+:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x[0-9a-f]+
-.*: file format elf32-.*arm
+.*: file format elf32-.*arm.*
architecture: arm, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
-.*: file format elf32-.*arm
+.*: file format elf32-.*arm.*
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
-.*: file format elf32-.*arm
+.*: file format elf32-.*arm.*
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
-.*: .*file format elf32-(big|little)arm
+.*: .*file format elf32-(big|little)arm.*
Disassembly of section \.text:
-.*: .*file format elf32-(big|little)arm
+.*: .*file format elf32-(big|little)arm.*
Disassembly of section \.text:
-.*: .*file format elf32-(big|little)arm
+.*: .*file format elf32-(big|little)arm.*
Disassembly of section \.text: