* 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)
* Another 24-bit (a second 2-bit XO) is needed for a planned future encoding, currently
named "SVP64-Single" [^likeext001]
-* A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved**comprehensive
+* A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved**
+ such that future unforeseen capability is needed.
* To hold all Vector Context, five SPRs are needed for userspace (MSR.PR=1 Problem State).
If Supervisor and Hypervisor mode are to also support Simple-V they will correspondingly
need five SPRs each.
+* Six 5/6-bit XO "Management" instructions are needed.
+
+**SPRs**
+
+* **SVSTATE** - Vectorisation State
+* **SVSRR0** - identical in purpose to SRR0/1, storing SVSTATE on context-switch
+* **SVSHAPE0-3* - these are 32-bit and may be grouped in pairs, they REMAP (shape)
+ the Vectors
+* **SVLR** - again similar to LR for exactly the same purpose, SVSTATE is swapped
+ with SVLR by SV-Branch-Conditional for exactly the same reason that NIA is swapped
+ with LR
# SVP64 24-bit Prefix
* Due to a concept called "Element-width Overrides
-[^extend]: Prefix opcode space **must** be reserved in advance to to so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2
+[^extend]: Prefix opcode space **must** be reserved in advance to do so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2
[^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact it still embeds v3.0 Scalar operations.