split out instructions from openpower/isa/fixedlogical.mdwn

diff --git a/openpower/isa/fixedlogical.mdwn b/openpower/isa/fixedlogical.mdwn
index 01eeffb1defc5255faea6b16c52a26e2c3a23bd4..6b578f17e17637b0db783712aedde0134d21e7a6 100644 (file)
--- a/openpower/isa/fixedlogical.mdwn
+++ b/openpower/isa/fixedlogical.mdwn
@@ -10,574 +10,68 @@
 <!-- instructions do not change the SO, OV, OV32, CA, and CA32 bits in the XER. -->
 
 
-# AND Immediate
+[[!inline pagenames="openpower/isa/fixedlogical/andi." raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedlogical/ori" raw="yes"]]
 
-* andi.  RA,RS,UI
+[[!inline pagenames="openpower/isa/fixedlogical/andis." raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedlogical/oris" raw="yes"]]
 
-    RA <- (RS) & EXTZ(UI)
+[[!inline pagenames="openpower/isa/fixedlogical/xoris" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedlogical/xori" raw="yes"]]
 
-    CR0
+[[!inline pagenames="openpower/isa/fixedlogical/and" raw="yes"]]
 
-# OR Immediate
+[[!inline pagenames="openpower/isa/fixedlogical/or" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedlogical/xor" raw="yes"]]
 
-* ori RA,RS,UI
+[[!inline pagenames="openpower/isa/fixedlogical/nand" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedlogical/nor" raw="yes"]]
 
-    RA <- (RS) | EXTZ(UI)
+[[!inline pagenames="openpower/isa/fixedlogical/eqv" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedlogical/andc" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedlogical/orc" raw="yes"]]
 
-# AND Immediate Shifted
+[[!inline pagenames="openpower/isa/fixedlogical/extsb" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedlogical/extsh" raw="yes"]]
 
-* andis.  RA,RS,UI
+[[!inline pagenames="openpower/isa/fixedlogical/cntlzw" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedlogical/cnttzw" raw="yes"]]
 
-    RA <- (RS) & EXTZ(UI || [0]*16)
+[[!inline pagenames="openpower/isa/fixedlogical/cmpb" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedlogical/popcntb" raw="yes"]]
 
-    CR0
+[[!inline pagenames="openpower/isa/fixedlogical/popcntw" raw="yes"]]
 
-# OR Immediate Shifted
+[[!inline pagenames="openpower/isa/fixedlogical/prtyd" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedlogical/prtyw" raw="yes"]]
 
-* oris      RA,RS,UI
+[[!inline pagenames="openpower/isa/fixedlogical/extsw" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedlogical/popcntd" raw="yes"]]
 
-    RA <- (RS) | EXTZ(UI || [0]*16)
+[[!inline pagenames="openpower/isa/fixedlogical/cntlzd" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedlogical/cnttzd" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedlogical/cntlzdm" raw="yes"]]
 
-# XOR Immediate Shifted
+[[!inline pagenames="openpower/isa/fixedlogical/cnttzdm" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedlogical/bpermd" raw="yes"]]
 
-* xoris RA,RS,UI
+[[!inline pagenames="openpower/isa/fixedlogical/cfuged" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedlogical/pextd" raw="yes"]]
 
-    RA <- (RS) ^ EXTZ(UI || [0]*16)
-
-Special Registers Altered:
-
-    None
-
-# XOR Immediate
-
-D-Form
-
-* xori RA,RS,UI
-
-Pseudo-code:
-
-    RA <- (RS) ^ EXTZ(UI)
-
-Special Registers Altered:
-
-    None
-
-# AND
-
-X-Form
-
-* and RA,RS,RB (Rc=0)
-* and.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    RA <- (RS) & (RB)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# OR
-
-X-Form
-
-* or RA,RS,RB (Rc=0)
-* or.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    RA <- (RS) | (RB)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# XOR
-
-X-Form
-
-* xor RA,RS,RB (Rc=0)
-* xor.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    RA <- (RS) ^ (RB)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# NAND
-
-X-Form
-
-* nand RA,RS,RB (Rc=0)
-* nand.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    RA <- ¬((RS) & (RB))
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# NOR
-
-X-Form
-
-* nor RA,RS,RB (Rc=0)
-* nor.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    RA <- ¬((RS) | (RB))
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Equivalent
-
-X-Form
-
-* eqv RA,RS,RB (Rc=0)
-* eqv.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    RA <- ¬((RS) ^ (RB))
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# AND with Complement
-
-X-Form
-
-* andc RA,RS,RB (Rc=0)
-* andc.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    RA <- (RS) &  ¬(RB)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# OR with Complement
-
-X-Form
-
-* orc RA,RS,RB (Rc=0)
-* orc.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    RA <- (RS) |  ¬(RB)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Extend Sign Byte
-
-X-Form
-
-* extsb RA,RS (Rc=0)
-* extsb.  RA,RS (Rc=1)
-
-Pseudo-code:
-
-    RA <- EXTSXL(RS, XLEN/8)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Extend Sign Halfword
-
-X-Form
-
-* extsh RA,RS (Rc=0)
-* extsh.  RA,RS (Rc=1)
-
-Pseudo-code:
-
-    RA <- EXTSXL(RS, XLEN/4)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Count Leading Zeros Word
-
-X-Form
-
-* cntlzw RA,RS (Rc=0)
-* cntlzw.  RA,RS (Rc=1)
-
-Pseudo-code:
-
-    n <- (XLEN/2)
-    do while n < XLEN
-       if (RS)[n] = 1 then
-           leave
-       n <- n + 1
-    RA <- n - (XLEN/2)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Count Trailing Zeros Word
-
-X-Form
-
-* cnttzw RA,RS (Rc=0)
-* cnttzw.  RA,RS (Rc=1)
-
-Pseudo-code:
-
-    n <- 0
-    do while n < XLEN/2
-       if (RS)[XLEN-1-n] = 0b1 then
-            leave
-       n  <- n + 1
-    RA <- EXTZ(n)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Compare Bytes
-
-X-Form
-
-* cmpb RA,RS,RB
-
-Pseudo-code:
-
-    do n = 0 to ((XLEN/8)-1)
-        if RS[8*n:8* n+7] = (RB)[8*n:8*n+7] then
-           RA[8*n:8* n+7] <- [1]*8
-        else
-           RA[8*n:8* n+7] <- [0]*8
-
-Special Registers Altered:
-
-    None
-
-# Population Count Bytes
-
-X-Form
-
-* popcntb RA,RS
-
-Pseudo-code:
-
-    do i = 0 to ((XLEN/8)-1)
-       n <-  0
-       do j = 0 to 7
-          if (RS)[(i*8)+j] = 1 then
-              n <- n+1
-       RA[(i*8):(i*8)+7] <-  n
-
-Special Registers Altered:
-
-    None
-
-# Population Count Words
-
-X-Form
-
-* popcntw RA,RS
-
-Pseudo-code:
-
-    e <- (XLEN/2)-1
-    do i = 0 to 1
-       s <- i*XLEN/2
-       n <-  0
-       do j = 0 to e
-          if (RS)[s+j] = 1 then
-              n <- n+1
-       RA[s:s+e] <- n
-
-Special Registers Altered:
-
-    None
-
-# Parity Doubleword
-
-X-Form
-
-* prtyd RA,RS
-
-Pseudo-code:
-
-    s <- 0
-    do i = 0 to ((XLEN/8)-1)
-        s <- s ^ (RS)[i*8+7]
-    RA <- [0] * (XLEN-1) || s
-
-Special Registers Altered:
-
-    None
-
-# Parity Word
-
-X-Form
-
-* prtyw RA,RS
-
-Pseudo-code:
-
-    s <- 0
-    t <- 0
-    do i = 0 to ((XLEN/8/2)-1)
-        s <-  s ^ (RS)[i*8+7]
-    do i = 4 to ((XLEN/8)-1)
-        t <-  t ^ (RS)[i*8+7]
-    RA[0:(XLEN/2)-1] <- [0]*((XLEN/2)-1) || s
-    RA[XLEN/2:XLEN-1] <- [0]*((XLEN/2)-1) || t
-
-Special Registers Altered:
-
-    None
-
-# Extend Sign Word
-
-X-Form
-
-* extsw RA,RS (Rc=0)
-* extsw.  RA,RS (Rc=1)
-
-Pseudo-code:
-
-    RA <- EXTSXL(RS, XLEN/2)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Population Count Doubleword
-
-X-Form
-
-* popcntd RA,RS
-
-Pseudo-code:
-
-    n <- 0
-    do i = 0 to (XLEN-1)
-       if (RS)[i] = 1 then
-           n <-  n+1
-    RA <- n
-
-Special Registers Altered:
-
-    None
-
-# Count Leading Zeros Doubleword
-
-X-Form
-
-* cntlzd RA,RS (Rc=0)
-* cntlzd.  RA,RS (Rc=1)
-
-Pseudo-code:
-
-    n <- 0
-    do while n < XLEN
-      if (RS)[n]  = 1 then
-         leave
-      n <- n + 1
-    RA <- n
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Count Trailing Zeros Doubleword
-
-X-Form
-
-* cnttzd RA,RS (Rc=0)
-* cnttzd.  RA,RS (Rc=1)
-
-Pseudo-code:
-
-    n  <- 0
-    do while n < XLEN
-       if (RS)[XLEN-1-n] = 0b1 then
-            leave
-       n  <- n + 1
-    RA <- EXTZ(n)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Count Leading Zeros Doubleword under bit Mask
-
-X-Form
-
-* cntlzdm RA,RS,RB
-
-Pseudo-code:
-
-    count <- 0
-    do i = 0 to 63
-        if (RB)[i] = 1 then
-            if (RS)[i] = 1 then leave
-            count <- count + 1
-    RA <- EXTZ64(count)
-
-Special Registers Altered:
-
-    None
-
-# Count Trailing Zeros Doubleword under bit Mask
-
-X-Form
-
-* cnttzdm RA,RS,RB
-
-Pseudo-code:
-
-    count <- 0
-    do i = 0 to 63
-        if (RB)[63-i] = 1 then
-            if (RS)[63-i] = 1 then leave
-            count <- count + 1
-    RA <- EXTZ64(count)
-
-Special Registers Altered:
-
-    None
-
-# Bit Permute Doubleword
-
-X-Form
-
-* bpermd RA,RS,RB
-
-Pseudo-code:
-
-    perm <- [0] * (XLEN/8)
-    for i = 0 to ((XLEN/8)-1)
-       index <- (RS)[8*i:8*i+7]
-       if index <u XLEN then
-            perm[i] <- (RB)[index]
-       else
-            perm[i] <- 0
-    RA <- [0]*(XLEN*7/8) || perm
-
-Special Registers Altered:
-
-    None
-
-# Centrifuge Doubleword
-
-X-Form
-
-* cfuged RA,RS,RB
-
-Pseudo-code:
-
-    ptr0 <- 0
-    ptr1 <- 0
-    result[0:63] <- 0
-    do i = 0 to 63
-        if (RB)[i] = 0 then
-            result[ptr0] <- (RS)[i]
-            ptr0 <- ptr0 + 1
-        if (RB)[63-i] = 1 then
-            result[63-ptr1] <- (RS)[63-i]
-            ptr1 <- ptr1 + 1
-    RA <- result
-
-Special Registers Altered:
-
-    None
-
-# Parallel Bits Extract Doubleword
-
-X-Form
-
-* pextd RA,RS,RB
-
-Pseudo-code:
-
-    result[0:63] <- 0
-    mask <- (RB)
-    m <- 0
-    k <- 0
-    do while m < 64
-        if (RB)[63-m] = 1 then
-            result[63-k] <- (RS)[63-m]
-            k <- k + 1
-        m <- m + 1
-    RA <- result
-
-Special Registers Altered:
-
-    None
-
-# Parallel Bits Deposit Doubleword
-
-X-Form
-
-* pdepd RA,RS,RB
-
-Pseudo-code:
-
-    result[0:63] <- 0
-    mask <- (RB)
-    m <- 0
-    k <- 0
-    do while m < 64
-        if (RB)[63-m] = 1 then
-            result[63-m] <- (RS)[63-k]
-            k <- k + 1
-        m <- m + 1
-    RA <- result
-
-Special Registers Altered:
-
-    None
+[[!inline pagenames="openpower/isa/fixedlogical/pdepd" raw="yes"]]

diff --git a/openpower/isa/fixedlogical/and.mdwn b/openpower/isa/fixedlogical/and.mdwn
new file mode 100644 (file)
index 0000000..b978dc4
--- /dev/null
+++ b/openpower/isa/fixedlogical/and.mdwn
@@ -0,0 +1,14 @@
+# AND
+
+X-Form
+
+* and RA,RS,RB (Rc=0)
+* and.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/and_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/and_code.mdwn b/openpower/isa/fixedlogical/and_code.mdwn
new file mode 100644 (file)
index 0000000..114430c
--- /dev/null
+++ b/openpower/isa/fixedlogical/and_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) & (RB)

diff --git a/openpower/isa/fixedlogical/andc.mdwn b/openpower/isa/fixedlogical/andc.mdwn
new file mode 100644 (file)
index 0000000..08dc944
--- /dev/null
+++ b/openpower/isa/fixedlogical/andc.mdwn
@@ -0,0 +1,14 @@
+# AND with Complement
+
+X-Form
+
+* andc RA,RS,RB (Rc=0)
+* andc.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/andc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/andc_code.mdwn b/openpower/isa/fixedlogical/andc_code.mdwn
new file mode 100644 (file)
index 0000000..9f01a18
--- /dev/null
+++ b/openpower/isa/fixedlogical/andc_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) &  ¬(RB)

diff --git a/openpower/isa/fixedlogical/andi..mdwn b/openpower/isa/fixedlogical/andi..mdwn
new file mode 100644 (file)
index 0000000..521dd0f
--- /dev/null
+++ b/openpower/isa/fixedlogical/andi..mdwn
@@ -0,0 +1,13 @@
+# AND Immediate
+
+D-Form
+
+* andi.  RA,RS,UI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/andi._code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0

diff --git a/openpower/isa/fixedlogical/andi._code.mdwn b/openpower/isa/fixedlogical/andi._code.mdwn
new file mode 100644 (file)
index 0000000..a9d1f90
--- /dev/null
+++ b/openpower/isa/fixedlogical/andi._code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) & EXTZ(UI)

diff --git a/openpower/isa/fixedlogical/andis..mdwn b/openpower/isa/fixedlogical/andis..mdwn
new file mode 100644 (file)
index 0000000..e3d1d50
--- /dev/null
+++ b/openpower/isa/fixedlogical/andis..mdwn
@@ -0,0 +1,13 @@
+# AND Immediate Shifted
+
+D-Form
+
+* andis.  RA,RS,UI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/andis._code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0

diff --git a/openpower/isa/fixedlogical/andis._code.mdwn b/openpower/isa/fixedlogical/andis._code.mdwn
new file mode 100644 (file)
index 0000000..b6d5e26
--- /dev/null
+++ b/openpower/isa/fixedlogical/andis._code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) & EXTZ(UI || [0]*16)

diff --git a/openpower/isa/fixedlogical/bpermd.mdwn b/openpower/isa/fixedlogical/bpermd.mdwn
new file mode 100644 (file)
index 0000000..8dad96a
--- /dev/null
+++ b/openpower/isa/fixedlogical/bpermd.mdwn
@@ -0,0 +1,13 @@
+# Bit Permute Doubleword
+
+X-Form
+
+* bpermd RA,RS,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/bpermd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/bpermd_code.mdwn b/openpower/isa/fixedlogical/bpermd_code.mdwn
new file mode 100644 (file)
index 0000000..3d21bcc
--- /dev/null
+++ b/openpower/isa/fixedlogical/bpermd_code.mdwn
@@ -0,0 +1,8 @@
+    perm <- [0] * (XLEN/8)
+    for i = 0 to ((XLEN/8)-1)
+       index <- (RS)[8*i:8*i+7]
+       if index <u XLEN then
+            perm[i] <- (RB)[index]
+       else
+            perm[i] <- 0
+    RA <- [0]*(XLEN*7/8) || perm

diff --git a/openpower/isa/fixedlogical/cfuged.mdwn b/openpower/isa/fixedlogical/cfuged.mdwn
new file mode 100644 (file)
index 0000000..50a5426
--- /dev/null
+++ b/openpower/isa/fixedlogical/cfuged.mdwn
@@ -0,0 +1,13 @@
+# Centrifuge Doubleword
+
+X-Form
+
+* cfuged RA,RS,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/cfuged_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/cfuged_code.mdwn b/openpower/isa/fixedlogical/cfuged_code.mdwn
new file mode 100644 (file)
index 0000000..9361e34
--- /dev/null
+++ b/openpower/isa/fixedlogical/cfuged_code.mdwn
@@ -0,0 +1,11 @@
+    ptr0 <- 0
+    ptr1 <- 0
+    result[0:63] <- 0
+    do i = 0 to 63
+        if (RB)[i] = 0 then
+            result[ptr0] <- (RS)[i]
+            ptr0 <- ptr0 + 1
+        if (RB)[63-i] = 1 then
+            result[63-ptr1] <- (RS)[63-i]
+            ptr1 <- ptr1 + 1
+    RA <- result

diff --git a/openpower/isa/fixedlogical/cmpb.mdwn b/openpower/isa/fixedlogical/cmpb.mdwn
new file mode 100644 (file)
index 0000000..1e4e21e
--- /dev/null
+++ b/openpower/isa/fixedlogical/cmpb.mdwn
@@ -0,0 +1,13 @@
+# Compare Bytes
+
+X-Form
+
+* cmpb RA,RS,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/cmpb_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/cmpb_code.mdwn b/openpower/isa/fixedlogical/cmpb_code.mdwn
new file mode 100644 (file)
index 0000000..da655d9
--- /dev/null
+++ b/openpower/isa/fixedlogical/cmpb_code.mdwn
@@ -0,0 +1,5 @@
+    do n = 0 to ((XLEN/8)-1)
+        if RS[8*n:8* n+7] = (RB)[8*n:8*n+7] then
+           RA[8*n:8* n+7] <- [1]*8
+        else
+           RA[8*n:8* n+7] <- [0]*8

diff --git a/openpower/isa/fixedlogical/cntlzd.mdwn b/openpower/isa/fixedlogical/cntlzd.mdwn
new file mode 100644 (file)
index 0000000..96c8b88
--- /dev/null
+++ b/openpower/isa/fixedlogical/cntlzd.mdwn
@@ -0,0 +1,14 @@
+# Count Leading Zeros Doubleword
+
+X-Form
+
+* cntlzd RA,RS (Rc=0)
+* cntlzd.  RA,RS (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/cntlzd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/cntlzd_code.mdwn b/openpower/isa/fixedlogical/cntlzd_code.mdwn
new file mode 100644 (file)
index 0000000..430ac85
--- /dev/null
+++ b/openpower/isa/fixedlogical/cntlzd_code.mdwn
@@ -0,0 +1,6 @@
+    n <- 0
+    do while n < XLEN
+      if (RS)[n]  = 1 then
+         leave
+      n <- n + 1
+    RA <- n

diff --git a/openpower/isa/fixedlogical/cntlzdm.mdwn b/openpower/isa/fixedlogical/cntlzdm.mdwn
new file mode 100644 (file)
index 0000000..bed921a
--- /dev/null
+++ b/openpower/isa/fixedlogical/cntlzdm.mdwn
@@ -0,0 +1,13 @@
+# Count Leading Zeros Doubleword under bit Mask
+
+X-Form
+
+* cntlzdm RA,RS,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/cntlzdm_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/cntlzdm_code.mdwn b/openpower/isa/fixedlogical/cntlzdm_code.mdwn
new file mode 100644 (file)
index 0000000..a780575
--- /dev/null
+++ b/openpower/isa/fixedlogical/cntlzdm_code.mdwn
@@ -0,0 +1,6 @@
+    count <- 0
+    do i = 0 to 63
+        if (RB)[i] = 1 then
+            if (RS)[i] = 1 then leave
+            count <- count + 1
+    RA <- EXTZ64(count)

diff --git a/openpower/isa/fixedlogical/cntlzw.mdwn b/openpower/isa/fixedlogical/cntlzw.mdwn
new file mode 100644 (file)
index 0000000..9e7b84c
--- /dev/null
+++ b/openpower/isa/fixedlogical/cntlzw.mdwn
@@ -0,0 +1,14 @@
+# Count Leading Zeros Word
+
+X-Form
+
+* cntlzw RA,RS (Rc=0)
+* cntlzw.  RA,RS (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/cntlzw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/cntlzw_code.mdwn b/openpower/isa/fixedlogical/cntlzw_code.mdwn
new file mode 100644 (file)
index 0000000..7f7985c
--- /dev/null
+++ b/openpower/isa/fixedlogical/cntlzw_code.mdwn
@@ -0,0 +1,6 @@
+    n <- (XLEN/2)
+    do while n < XLEN
+       if (RS)[n] = 1 then
+           leave
+       n <- n + 1
+    RA <- n - (XLEN/2)

diff --git a/openpower/isa/fixedlogical/cnttzd.mdwn b/openpower/isa/fixedlogical/cnttzd.mdwn
new file mode 100644 (file)
index 0000000..948b898
--- /dev/null
+++ b/openpower/isa/fixedlogical/cnttzd.mdwn
@@ -0,0 +1,14 @@
+# Count Trailing Zeros Doubleword
+
+X-Form
+
+* cnttzd RA,RS (Rc=0)
+* cnttzd.  RA,RS (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/cnttzd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/cnttzd_code.mdwn b/openpower/isa/fixedlogical/cnttzd_code.mdwn
new file mode 100644 (file)
index 0000000..f5b913a
--- /dev/null
+++ b/openpower/isa/fixedlogical/cnttzd_code.mdwn
@@ -0,0 +1,6 @@
+    n  <- 0
+    do while n < XLEN
+       if (RS)[XLEN-1-n] = 0b1 then
+            leave
+       n  <- n + 1
+    RA <- EXTZ(n)

diff --git a/openpower/isa/fixedlogical/cnttzdm.mdwn b/openpower/isa/fixedlogical/cnttzdm.mdwn
new file mode 100644 (file)
index 0000000..41cb83b
--- /dev/null
+++ b/openpower/isa/fixedlogical/cnttzdm.mdwn
@@ -0,0 +1,13 @@
+# Count Trailing Zeros Doubleword under bit Mask
+
+X-Form
+
+* cnttzdm RA,RS,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/cnttzdm_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/cnttzdm_code.mdwn b/openpower/isa/fixedlogical/cnttzdm_code.mdwn
new file mode 100644 (file)
index 0000000..413cb85
--- /dev/null
+++ b/openpower/isa/fixedlogical/cnttzdm_code.mdwn
@@ -0,0 +1,6 @@
+    count <- 0
+    do i = 0 to 63
+        if (RB)[63-i] = 1 then
+            if (RS)[63-i] = 1 then leave
+            count <- count + 1
+    RA <- EXTZ64(count)

diff --git a/openpower/isa/fixedlogical/cnttzw.mdwn b/openpower/isa/fixedlogical/cnttzw.mdwn
new file mode 100644 (file)
index 0000000..e9e8ec9
--- /dev/null
+++ b/openpower/isa/fixedlogical/cnttzw.mdwn
@@ -0,0 +1,14 @@
+# Count Trailing Zeros Word
+
+X-Form
+
+* cnttzw RA,RS (Rc=0)
+* cnttzw.  RA,RS (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/cnttzw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/cnttzw_code.mdwn b/openpower/isa/fixedlogical/cnttzw_code.mdwn
new file mode 100644 (file)
index 0000000..a6a7d1e
--- /dev/null
+++ b/openpower/isa/fixedlogical/cnttzw_code.mdwn
@@ -0,0 +1,6 @@
+    n <- 0
+    do while n < XLEN/2
+       if (RS)[XLEN-1-n] = 0b1 then
+            leave
+       n  <- n + 1
+    RA <- EXTZ(n)

diff --git a/openpower/isa/fixedlogical/eqv.mdwn b/openpower/isa/fixedlogical/eqv.mdwn
new file mode 100644 (file)
index 0000000..6badb4b
--- /dev/null
+++ b/openpower/isa/fixedlogical/eqv.mdwn
@@ -0,0 +1,14 @@
+# Equivalent
+
+X-Form
+
+* eqv RA,RS,RB (Rc=0)
+* eqv.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/eqv_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/eqv_code.mdwn b/openpower/isa/fixedlogical/eqv_code.mdwn
new file mode 100644 (file)
index 0000000..0923685
--- /dev/null
+++ b/openpower/isa/fixedlogical/eqv_code.mdwn
@@ -0,0 +1 @@
+    RA <- ¬((RS) ^ (RB))

diff --git a/openpower/isa/fixedlogical/extsb.mdwn b/openpower/isa/fixedlogical/extsb.mdwn
new file mode 100644 (file)
index 0000000..30e4dd0
--- /dev/null
+++ b/openpower/isa/fixedlogical/extsb.mdwn
@@ -0,0 +1,14 @@
+# Extend Sign Byte
+
+X-Form
+
+* extsb RA,RS (Rc=0)
+* extsb.  RA,RS (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/extsb_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/extsb_code.mdwn b/openpower/isa/fixedlogical/extsb_code.mdwn
new file mode 100644 (file)
index 0000000..ed026d7
--- /dev/null
+++ b/openpower/isa/fixedlogical/extsb_code.mdwn
@@ -0,0 +1 @@
+    RA <- EXTSXL(RS, XLEN/8)

diff --git a/openpower/isa/fixedlogical/extsh.mdwn b/openpower/isa/fixedlogical/extsh.mdwn
new file mode 100644 (file)
index 0000000..6e8ab5b
--- /dev/null
+++ b/openpower/isa/fixedlogical/extsh.mdwn
@@ -0,0 +1,14 @@
+# Extend Sign Halfword
+
+X-Form
+
+* extsh RA,RS (Rc=0)
+* extsh.  RA,RS (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/extsh_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/extsh_code.mdwn b/openpower/isa/fixedlogical/extsh_code.mdwn
new file mode 100644 (file)
index 0000000..653680b
--- /dev/null
+++ b/openpower/isa/fixedlogical/extsh_code.mdwn
@@ -0,0 +1 @@
+    RA <- EXTSXL(RS, XLEN/4)

diff --git a/openpower/isa/fixedlogical/extsw.mdwn b/openpower/isa/fixedlogical/extsw.mdwn
new file mode 100644 (file)
index 0000000..5b59776
--- /dev/null
+++ b/openpower/isa/fixedlogical/extsw.mdwn
@@ -0,0 +1,14 @@
+# Extend Sign Word
+
+X-Form
+
+* extsw RA,RS (Rc=0)
+* extsw.  RA,RS (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/extsw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/extsw_code.mdwn b/openpower/isa/fixedlogical/extsw_code.mdwn
new file mode 100644 (file)
index 0000000..8353e53
--- /dev/null
+++ b/openpower/isa/fixedlogical/extsw_code.mdwn
@@ -0,0 +1 @@
+    RA <- EXTSXL(RS, XLEN/2)

diff --git a/openpower/isa/fixedlogical/nand.mdwn b/openpower/isa/fixedlogical/nand.mdwn
new file mode 100644 (file)
index 0000000..e87c121
--- /dev/null
+++ b/openpower/isa/fixedlogical/nand.mdwn
@@ -0,0 +1,14 @@
+# NAND
+
+X-Form
+
+* nand RA,RS,RB (Rc=0)
+* nand.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/nand_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/nand_code.mdwn b/openpower/isa/fixedlogical/nand_code.mdwn
new file mode 100644 (file)
index 0000000..fbfec92
--- /dev/null
+++ b/openpower/isa/fixedlogical/nand_code.mdwn
@@ -0,0 +1 @@
+    RA <- ¬((RS) & (RB))

diff --git a/openpower/isa/fixedlogical/nor.mdwn b/openpower/isa/fixedlogical/nor.mdwn
new file mode 100644 (file)
index 0000000..5833ed0
--- /dev/null
+++ b/openpower/isa/fixedlogical/nor.mdwn
@@ -0,0 +1,14 @@
+# NOR
+
+X-Form
+
+* nor RA,RS,RB (Rc=0)
+* nor.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/nor_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/nor_code.mdwn b/openpower/isa/fixedlogical/nor_code.mdwn
new file mode 100644 (file)
index 0000000..8ca9749
--- /dev/null
+++ b/openpower/isa/fixedlogical/nor_code.mdwn
@@ -0,0 +1 @@
+    RA <- ¬((RS) | (RB))

diff --git a/openpower/isa/fixedlogical/or.mdwn b/openpower/isa/fixedlogical/or.mdwn
new file mode 100644 (file)
index 0000000..4a7b009
--- /dev/null
+++ b/openpower/isa/fixedlogical/or.mdwn
@@ -0,0 +1,14 @@
+# OR
+
+X-Form
+
+* or RA,RS,RB (Rc=0)
+* or.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/or_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/or_code.mdwn b/openpower/isa/fixedlogical/or_code.mdwn
new file mode 100644 (file)
index 0000000..adb5ba2
--- /dev/null
+++ b/openpower/isa/fixedlogical/or_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) | (RB)

diff --git a/openpower/isa/fixedlogical/orc.mdwn b/openpower/isa/fixedlogical/orc.mdwn
new file mode 100644 (file)
index 0000000..d99a651
--- /dev/null
+++ b/openpower/isa/fixedlogical/orc.mdwn
@@ -0,0 +1,14 @@
+# OR with Complement
+
+X-Form
+
+* orc RA,RS,RB (Rc=0)
+* orc.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/orc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/orc_code.mdwn b/openpower/isa/fixedlogical/orc_code.mdwn
new file mode 100644 (file)
index 0000000..59823bc
--- /dev/null
+++ b/openpower/isa/fixedlogical/orc_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) |  ¬(RB)

diff --git a/openpower/isa/fixedlogical/ori.mdwn b/openpower/isa/fixedlogical/ori.mdwn
new file mode 100644 (file)
index 0000000..7c5b359
--- /dev/null
+++ b/openpower/isa/fixedlogical/ori.mdwn
@@ -0,0 +1,13 @@
+# OR Immediate
+
+D-Form
+
+* ori RA,RS,UI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/ori_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/ori_code.mdwn b/openpower/isa/fixedlogical/ori_code.mdwn
new file mode 100644 (file)
index 0000000..20dd488
--- /dev/null
+++ b/openpower/isa/fixedlogical/ori_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) | EXTZ(UI)

diff --git a/openpower/isa/fixedlogical/oris.mdwn b/openpower/isa/fixedlogical/oris.mdwn
new file mode 100644 (file)
index 0000000..fa1dcc8
--- /dev/null
+++ b/openpower/isa/fixedlogical/oris.mdwn
@@ -0,0 +1,13 @@
+# OR Immediate Shifted
+
+D-Form
+
+* oris      RA,RS,UI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/oris_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/oris_code.mdwn b/openpower/isa/fixedlogical/oris_code.mdwn
new file mode 100644 (file)
index 0000000..9d60d3a
--- /dev/null
+++ b/openpower/isa/fixedlogical/oris_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) | EXTZ(UI || [0]*16)

diff --git a/openpower/isa/fixedlogical/pdepd.mdwn b/openpower/isa/fixedlogical/pdepd.mdwn
new file mode 100644 (file)
index 0000000..658594c
--- /dev/null
+++ b/openpower/isa/fixedlogical/pdepd.mdwn
@@ -0,0 +1,13 @@
+# Parallel Bits Deposit Doubleword
+
+X-Form
+
+* pdepd RA,RS,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/pdepd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/pdepd_code.mdwn b/openpower/isa/fixedlogical/pdepd_code.mdwn
new file mode 100644 (file)
index 0000000..e01b270
--- /dev/null
+++ b/openpower/isa/fixedlogical/pdepd_code.mdwn
@@ -0,0 +1,10 @@
+    result[0:63] <- 0
+    mask <- (RB)
+    m <- 0
+    k <- 0
+    do while m < 64
+        if (RB)[63-m] = 1 then
+            result[63-m] <- (RS)[63-k]
+            k <- k + 1
+        m <- m + 1
+    RA <- result

diff --git a/openpower/isa/fixedlogical/pextd.mdwn b/openpower/isa/fixedlogical/pextd.mdwn
new file mode 100644 (file)
index 0000000..717fa93
--- /dev/null
+++ b/openpower/isa/fixedlogical/pextd.mdwn
@@ -0,0 +1,13 @@
+# Parallel Bits Extract Doubleword
+
+X-Form
+
+* pextd RA,RS,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/pextd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/pextd_code.mdwn b/openpower/isa/fixedlogical/pextd_code.mdwn
new file mode 100644 (file)
index 0000000..24f918a
--- /dev/null
+++ b/openpower/isa/fixedlogical/pextd_code.mdwn
@@ -0,0 +1,10 @@
+    result[0:63] <- 0
+    mask <- (RB)
+    m <- 0
+    k <- 0
+    do while m < 64
+        if (RB)[63-m] = 1 then
+            result[63-k] <- (RS)[63-m]
+            k <- k + 1
+        m <- m + 1
+    RA <- result

diff --git a/openpower/isa/fixedlogical/popcntb.mdwn b/openpower/isa/fixedlogical/popcntb.mdwn
new file mode 100644 (file)
index 0000000..bb76499
--- /dev/null
+++ b/openpower/isa/fixedlogical/popcntb.mdwn
@@ -0,0 +1,13 @@
+# Population Count Bytes
+
+X-Form
+
+* popcntb RA,RS
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/popcntb_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/popcntb_code.mdwn b/openpower/isa/fixedlogical/popcntb_code.mdwn
new file mode 100644 (file)
index 0000000..13f7c94
--- /dev/null
+++ b/openpower/isa/fixedlogical/popcntb_code.mdwn
@@ -0,0 +1,6 @@
+    do i = 0 to ((XLEN/8)-1)
+       n <-  0
+       do j = 0 to 7
+          if (RS)[(i*8)+j] = 1 then
+              n <- n+1
+       RA[(i*8):(i*8)+7] <-  n

diff --git a/openpower/isa/fixedlogical/popcntd.mdwn b/openpower/isa/fixedlogical/popcntd.mdwn
new file mode 100644 (file)
index 0000000..7c07d52
--- /dev/null
+++ b/openpower/isa/fixedlogical/popcntd.mdwn
@@ -0,0 +1,13 @@
+# Population Count Doubleword
+
+X-Form
+
+* popcntd RA,RS
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/popcntd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/popcntd_code.mdwn b/openpower/isa/fixedlogical/popcntd_code.mdwn
new file mode 100644 (file)
index 0000000..c489da8
--- /dev/null
+++ b/openpower/isa/fixedlogical/popcntd_code.mdwn
@@ -0,0 +1,5 @@
+    n <- 0
+    do i = 0 to (XLEN-1)
+       if (RS)[i] = 1 then
+           n <-  n+1
+    RA <- n

diff --git a/openpower/isa/fixedlogical/popcntw.mdwn b/openpower/isa/fixedlogical/popcntw.mdwn
new file mode 100644 (file)
index 0000000..03797ff
--- /dev/null
+++ b/openpower/isa/fixedlogical/popcntw.mdwn
@@ -0,0 +1,13 @@
+# Population Count Words
+
+X-Form
+
+* popcntw RA,RS
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/popcntw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/popcntw_code.mdwn b/openpower/isa/fixedlogical/popcntw_code.mdwn
new file mode 100644 (file)
index 0000000..980ed9f
--- /dev/null
+++ b/openpower/isa/fixedlogical/popcntw_code.mdwn
@@ -0,0 +1,8 @@
+    e <- (XLEN/2)-1
+    do i = 0 to 1
+       s <- i*XLEN/2
+       n <-  0
+       do j = 0 to e
+          if (RS)[s+j] = 1 then
+              n <- n+1
+       RA[s:s+e] <- n

diff --git a/openpower/isa/fixedlogical/prtyd.mdwn b/openpower/isa/fixedlogical/prtyd.mdwn
new file mode 100644 (file)
index 0000000..6ebc570
--- /dev/null
+++ b/openpower/isa/fixedlogical/prtyd.mdwn
@@ -0,0 +1,13 @@
+# Parity Doubleword
+
+X-Form
+
+* prtyd RA,RS
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/prtyd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/prtyd_code.mdwn b/openpower/isa/fixedlogical/prtyd_code.mdwn
new file mode 100644 (file)
index 0000000..1243775
--- /dev/null
+++ b/openpower/isa/fixedlogical/prtyd_code.mdwn
@@ -0,0 +1,4 @@
+    s <- 0
+    do i = 0 to ((XLEN/8)-1)
+        s <- s ^ (RS)[i*8+7]
+    RA <- [0] * (XLEN-1) || s

diff --git a/openpower/isa/fixedlogical/prtyw.mdwn b/openpower/isa/fixedlogical/prtyw.mdwn
new file mode 100644 (file)
index 0000000..016c95e
--- /dev/null
+++ b/openpower/isa/fixedlogical/prtyw.mdwn
@@ -0,0 +1,13 @@
+# Parity Word
+
+X-Form
+
+* prtyw RA,RS
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/prtyw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/prtyw_code.mdwn b/openpower/isa/fixedlogical/prtyw_code.mdwn
new file mode 100644 (file)
index 0000000..3955046
--- /dev/null
+++ b/openpower/isa/fixedlogical/prtyw_code.mdwn
@@ -0,0 +1,8 @@
+    s <- 0
+    t <- 0
+    do i = 0 to ((XLEN/8/2)-1)
+        s <-  s ^ (RS)[i*8+7]
+    do i = 4 to ((XLEN/8)-1)
+        t <-  t ^ (RS)[i*8+7]
+    RA[0:(XLEN/2)-1] <- [0]*((XLEN/2)-1) || s
+    RA[XLEN/2:XLEN-1] <- [0]*((XLEN/2)-1) || t

diff --git a/openpower/isa/fixedlogical/xor.mdwn b/openpower/isa/fixedlogical/xor.mdwn
new file mode 100644 (file)
index 0000000..2586548
--- /dev/null
+++ b/openpower/isa/fixedlogical/xor.mdwn
@@ -0,0 +1,14 @@
+# XOR
+
+X-Form
+
+* xor RA,RS,RB (Rc=0)
+* xor.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/xor_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedlogical/xor_code.mdwn b/openpower/isa/fixedlogical/xor_code.mdwn
new file mode 100644 (file)
index 0000000..b9f19dd
--- /dev/null
+++ b/openpower/isa/fixedlogical/xor_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) ^ (RB)

diff --git a/openpower/isa/fixedlogical/xori.mdwn b/openpower/isa/fixedlogical/xori.mdwn
new file mode 100644 (file)
index 0000000..5ec8eb2
--- /dev/null
+++ b/openpower/isa/fixedlogical/xori.mdwn
@@ -0,0 +1,13 @@
+# XOR Immediate
+
+D-Form
+
+* xori RA,RS,UI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/xori_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/xori_code.mdwn b/openpower/isa/fixedlogical/xori_code.mdwn
new file mode 100644 (file)
index 0000000..8fdfbee
--- /dev/null
+++ b/openpower/isa/fixedlogical/xori_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) ^ EXTZ(UI)

diff --git a/openpower/isa/fixedlogical/xoris.mdwn b/openpower/isa/fixedlogical/xoris.mdwn
new file mode 100644 (file)
index 0000000..d50ee1a
--- /dev/null
+++ b/openpower/isa/fixedlogical/xoris.mdwn
@@ -0,0 +1,13 @@
+# XOR Immediate Shifted
+
+D-Form
+
+* xoris RA,RS,UI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedlogical/xoris_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedlogical/xoris_code.mdwn b/openpower/isa/fixedlogical/xoris_code.mdwn
new file mode 100644 (file)
index 0000000..c728d9b
--- /dev/null
+++ b/openpower/isa/fixedlogical/xoris_code.mdwn
@@ -0,0 +1 @@
+    RA <- (RS) ^ EXTZ(UI || [0]*16)