intel: genxml: add preemption control instructions

Helpful to debug kernel workaround batchbuffers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index aeb9966759270fcf872717cd615688ee2df60587..bd914ad10ee5bc8fda7424741c697bce2b5c2d8b 100644 (file)
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -2824,6 +2824,13 @@
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
   </instruction>
 
+  <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+    <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+    <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+    <field name="Allow Lite Restore" start="1" end="1" type="bool"/>
+    <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+  </instruction>
+
   <instruction name="MI_ATOMIC" bias="2" length="3">
     <field name="Command Type" start="29" end="31" type="uint" default="0"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 6ca0e785ba0f809957bec48b0ee8a74957cf95eb..cb3212620f521c68aa3fc1b3fd08ef5e38d42622 100644 (file)
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -2788,6 +2788,13 @@
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
   </instruction>
 
+  <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+    <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+    <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+    <field name="Allow Lite Restore" start="1" end="1" type="bool"/>
+    <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+  </instruction>
+
   <instruction name="MI_ATOMIC" bias="2" length="3">
     <field name="Command Type" start="29" end="31" type="uint" default="0"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 71626c15cd2f92957c16a7baff9345d34ed815f7..28fbdfdf09a04cb86bfb67a8af10343c26b1252d 100644 (file)
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2509,6 +2509,12 @@
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
   </instruction>
 
+  <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+    <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+    <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+    <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+  </instruction>
+
   <instruction name="MI_ATOMIC" bias="2" length="3">
     <field name="Command Type" start="29" end="31" type="uint" default="0"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index c32f2c3162c5f3fdd4d2135f5b8044b8e2e8c3a9..0912b6f7fe42689946580bab4d2bd6e38f7995aa 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2752,6 +2752,12 @@
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
   </instruction>
 
+  <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+    <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+    <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+    <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+  </instruction>
+
   <instruction name="MI_ATOMIC" bias="2" length="3">
     <field name="Command Type" start="29" end="31" type="uint" default="0"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>