examples/../top: update

diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py
index 92454650e1e4fe91a7aa716d6fca773c86d25e86..f52d73469fab927eda5755eb140d4d9b58bed59a 100644 (file)
--- a/examples/de0_nano/top.py
+++ b/examples/de0_nano/top.py
@@ -7,23 +7,23 @@
 #
 #      Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
 #
-#                  migScope Example on De0 Nano Board
+#                  miscope Example on De0 Nano Board
 #                  ----------------------------------
 ################################################################################
 #
 # In this example signals are generated in the FPGA. 
-# We will use migScope to record those signals and visualize them.
+# We use miscope to record those signals and visualize them.
 # 
 # Example architecture:
 # ----------------------
-#        migScope Config  --> Python Client (Host) --> Vcd Output
+#        miscope Config  --> Python Client (Host) --> Vcd Output
 #             & Trig                |
 #                        Arduino (Uart<-->Spi Bridge)
 #                                   |
 #                                De0 Nano
 #                                   |
 #              +--------------------+-----------------------+  
-#            migIo             Signal Generator           migLa
+#            miIo             Signal Generator           miLa
 #       Control of Signal        Ramp, Sinus,           Logic Analyzer  
 #           generator            Square, ...
 ###############################################################################
@@ -39,10 +39,10 @@ from migen.bus.transactions import *
 from migen.bank import description, csrgen
 from migen.bank.description import *
 
+from miscope import trigger, recorder, miIo, miLa
+
 import sys
 sys.path.append("../../")
-
-from migScope import trigger, recorder, migIo, migLa
 import spi2Csr
 
 from timings import *
@@ -70,9 +70,9 @@ dat1_width = 32
 record_size = 4096
 
 # Csr Addr
-MIGIO0_ADDR  = 0x0000
-MIGLA0_ADDR  = 0x0200
-MIGLA1_ADDR  = 0x0600
+MIIO0_ADDR  = 0x0000
+MILA0_ADDR  = 0x0200
+MILA1_ADDR  = 0x0600
 
 #==============================================================================
 #       M I S C O P E    E X A M P L E
@@ -80,21 +80,21 @@ MIGLA1_ADDR  = 0x0600
 def get():
 
        # migIo0
-       migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO")
+       miIo0 = miIo.MiIo(MIIO0_ADDR, 8, "IO")
        
        # migLa0
        term0 = trigger.Term(trig0_width)
        trigger0 = trigger.Trigger(trig0_width, [term0])
        recorder0 = recorder.Recorder(dat0_width, record_size)
        
-       migLa0 = migLa.MigLa(MIGLA0_ADDR, trigger0, recorder0)
+       miLa0 = miLa.MiLa(MILA0_ADDR, trigger0, recorder0)
        
        # migLa1
        term1 = trigger.Term(trig1_width)
        trigger1 = trigger.Trigger(trig1_width, [term1])
        recorder1 = recorder.Recorder(dat1_width, record_size)
        
-       migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1)
+       miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1)
        
        # Spi2Csr
        spi2csr0 = spi2Csr.Spi2Csr(16,8)
@@ -102,11 +102,11 @@ def get():
        # Csr Interconnect
        csrcon0 = csr.Interconnect(spi2csr0.csr, 
                        [
-                               migIo0.bank.bus,
-                               migLa0.trig.bank.bus,
-                               migLa0.rec.bank.bus,
-                               migLa1.trig.bank.bus,
-                               migLa1.rec.bank.bus,
+                               miIo0.bank.bus,
+                               miLa0.trig.bank.bus,
+                               miLa0.rec.bank.bus,
+                               miLa1.trig.bank.bus,
+                               miLa1.rec.bank.bus,
                                
                        ])
        comb = []
@@ -147,11 +147,11 @@ def get():
        # Signal Selection
        sig_gen = Signal(8)
        comb += [
-               If(migIo0.o == 0,
+               If(miIo0.o == 0,
                        sig_gen.eq(cnt_gen)
-               ).Elif(migIo0.o == 1,
+               ).Elif(miIo0.o == 1,
                        sig_gen.eq(square_gen)
-               ).Elif(migIo0.o == 2,
+               ).Elif(miIo0.o == 2,
                        sig_gen.eq(sinus_gen)
                ).Else(
                        sig_gen.eq(0)
@@ -160,23 +160,23 @@ def get():
        
        # Led
        led0 = Signal(8)
-       comb += [led0.eq(migIo0.o[:8])]
+       comb += [led0.eq(miIo0.o[:8])]
        
        
        # MigLa0 input
        comb += [
-               migLa0.in_trig.eq(sig_gen),
-               migLa0.in_dat.eq(sig_gen)
+               miLa0.in_trig.eq(sig_gen),
+               miLa0.in_dat.eq(sig_gen)
        ]
        
        # MigLa1 input
        comb += [
-               migLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
-               migLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
-               migLa1.in_trig[24].eq(spi2csr0.csr.we),
-               migLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
-               migLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
-               migLa1.in_dat[24].eq(spi2csr0.csr.we)
+               miLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
+               miLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
+               miLa1.in_trig[24].eq(spi2csr0.csr.we),
+               miLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
+               miLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
+               miLa1.in_dat[24].eq(spi2csr0.csr.we)
        ]
        
        

diff --git a/examples/de1/top.py b/examples/de1/top.py
index b8711a2ba422d437f99ef22f2086c8ff43de0977..e10feaaa1544453cb860430405341f7e5bf2887c 100644 (file)
--- a/examples/de1/top.py
+++ b/examples/de1/top.py
@@ -7,23 +7,23 @@
 #
 #      Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
 #
-#                    migScope Example on De1 Board
+#                    miscope Example on De1 Board
 #                  ----------------------------------
 ################################################################################
 #
 # In this example signals are generated in the FPGA. 
-# We will use migScope to record those signals and visualize them.
+# We use miscope to record those signals and visualize them.
 # 
 # Example architecture:
 # ----------------------
-#        migScope Config  --> Python Client (Host) --> Vcd Output
+#        miscope Config  --> Python Client (Host) --> Vcd Output
 #             & Trig                |
 #                        Arduino (Uart<-->Spi Bridge)
 #                                   |
 #                                  De1 
 #                                   |
 #              +--------------------+-----------------------+  
-#            migIo             Signal Generator           migLa
+#            miIo             Signal Generator           miLa
 #       Control of Signal        Ramp, Sinus,           Logic Analyzer  
 #           generator            Square, ...
 ###############################################################################
@@ -39,10 +39,10 @@ from migen.bus.transactions import *
 from migen.bank import description, csrgen
 from migen.bank.description import *
 
+from miscope import trigger, recorder, miIo, miLa
+
 import sys
 sys.path.append("../../")
-
-from migScope import trigger, recorder, migIo, migLa
 import spi2Csr
 
 from timings import *
@@ -70,9 +70,9 @@ dat1_width = 32
 record_size = 4096
 
 # Csr Addr
-MIGIO0_ADDR  = 0x0000
-MIGLA0_ADDR  = 0x0200
-MIGLA1_ADDR  = 0x0600
+MIIO0_ADDR  = 0x0000
+MILA0_ADDR  = 0x0200
+MILA1_ADDR  = 0x0600
 
 #==============================================================================
 #       M I S C O P E    E X A M P L E
@@ -80,21 +80,21 @@ MIGLA1_ADDR  = 0x0600
 def get():
 
        # migIo0
-       migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO")
+       miIo0 = miIo.MiIo(MIIO0_ADDR, 8, "IO")
        
        # migLa0
        term0 = trigger.Term(trig0_width)
        trigger0 = trigger.Trigger(trig0_width, [term0])
        recorder0 = recorder.Recorder(dat0_width, record_size)
        
-       migLa0 = migLa.MigLa(MIGLA0_ADDR, trigger0, recorder0)
+       miLa0 = miLa.MiLa(MILA0_ADDR, trigger0, recorder0)
        
        # migLa1
        term1 = trigger.Term(trig1_width)
        trigger1 = trigger.Trigger(trig1_width, [term1])
        recorder1 = recorder.Recorder(dat1_width, record_size)
        
-       migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1)
+       miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1)
        
        # Spi2Csr
        spi2csr0 = spi2Csr.Spi2Csr(16,8)
@@ -102,11 +102,11 @@ def get():
        # Csr Interconnect
        csrcon0 = csr.Interconnect(spi2csr0.csr, 
                        [
-                               migIo0.bank.bus,
-                               migLa0.trig.bank.bus,
-                               migLa0.rec.bank.bus,
-                               migLa1.trig.bank.bus,
-                               migLa1.rec.bank.bus,
+                               miIo0.bank.bus,
+                               miLa0.trig.bank.bus,
+                               miLa0.rec.bank.bus,
+                               miLa1.trig.bank.bus,
+                               miLa1.rec.bank.bus,
                                
                        ])
        comb = []
@@ -147,11 +147,11 @@ def get():
        # Signal Selection
        sig_gen = Signal(8)
        comb += [
-               If(migIo0.o == 0,
+               If(miIo0.o == 0,
                        sig_gen.eq(cnt_gen)
-               ).Elif(migIo0.o == 1,
+               ).Elif(miIo0.o == 1,
                        sig_gen.eq(square_gen)
-               ).Elif(migIo0.o == 2,
+               ).Elif(miIo0.o == 2,
                        sig_gen.eq(sinus_gen)
                ).Else(
                        sig_gen.eq(0)
@@ -160,26 +160,26 @@ def get():
        
        # Led
        led0 = Signal(8)
-       comb += [led0.eq(migIo0.o[:8])]
+       comb += [led0.eq(miIo0.o[:8])]
        
        #Switch
        sw0 = Signal(8)
-       comb += [migIo0.i.eq(sw0)]
+       comb += [miIo0.i.eq(sw0)]
        
        # MigLa0 input
        comb += [
-               migLa0.in_trig.eq(sig_gen),
-               migLa0.in_dat.eq(sig_gen)
+               miLa0.in_trig.eq(sig_gen),
+               miLa0.in_dat.eq(sig_gen)
        ]
        
        # MigLa1 input
        comb += [
-               migLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
-               migLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
-               migLa1.in_trig[24].eq(spi2csr0.csr.we),
-               migLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
-               migLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
-               migLa1.in_dat[24].eq(spi2csr0.csr.we)
+               miLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
+               miLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
+               miLa1.in_trig[24].eq(spi2csr0.csr.we),
+               miLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
+               miLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
+               miLa1.in_dat[24].eq(spi2csr0.csr.we)
        ]