Fix handling of empty cell port assignments (i.e. ignore them)

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index d71e9c574bdd3af9bcb91f570488b587f7e7596a..41c1cfdedba0c414f605ae96eed667c92b512fd2 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -640,6 +640,9 @@ struct HierarchyPass : public Pass {
                                        if (w == nullptr || w->port_id == 0)
                                                continue;
 
+                                       if (GetSize(conn.second) == 0)
+                                               continue;
+
                                        if (GetSize(w) == GetSize(conn.second))
                                                continue;
 

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index e85714b5798eb309974392d7558e447c85f7ceae..ae89453d0587508d17a26b29d0f0f323174f4d2c 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -247,6 +247,9 @@ struct TechmapWorker
                                continue;
                        }
 
+                       if (GetSize(it.second) == 0)
+                               continue;
+
                        RTLIL::Wire *w = tpl->wires_.at(portname);
                        RTLIL::SigSig c, extra_connect;