pan/midgard: Fix flipped register bias fields

We mixed up component_lo and full, which made it appear that we had
less freedom in RA than we actually do. Fix this to fix some
disassemblies as well as prepare for RA with the bias field.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

diff --git a/src/panfrost/midgard/disassemble.c b/src/panfrost/midgard/disassemble.c
index 7fb5d202cc3a1f4213444518b83a2bc7eb2e1d2c..acc1f408e98a30470322fac3f1d6015d62702934 100644 (file)
--- a/src/panfrost/midgard/disassemble.c
+++ b/src/panfrost/midgard/disassemble.c
@@ -1206,14 +1206,9 @@ print_texture_word(uint32_t *word, unsigned tabs)
                 uint8_t raw = texture->bias;
                 memcpy(&sel, &raw, sizeof(raw));
 
-                unsigned c = (sel.component_hi << 1) | sel.component_lo;
-
                 printf("lod %c ", lod_operand);
                 print_texture_reg(sel.full, sel.select, sel.upper);
-                printf(".%c, ", components[c]);
-
-                if (!sel.component_hi)
-                        printf(" /* gradient? */");
+                printf(".%c, ", components[sel.component]);
 
                 if (texture->bias_int)
                         printf(" /* bias_int = 0x%X */", texture->bias_int);

diff --git a/src/panfrost/midgard/midgard.h b/src/panfrost/midgard/midgard.h
index 311f3bc043ad8ab342537ae9a6ebe7efde60ff68..84b9aa2fe08a32f57eac867b7a040a07c5ef4148 100644 (file)
--- a/src/panfrost/midgard/midgard.h
+++ b/src/panfrost/midgard/midgard.h
@@ -516,11 +516,8 @@ midgard_load_store;
 typedef struct
 __attribute__((__packed__))
 {
-        /* Combines with component_hi to form 2-bit component select out of
-         * xyzw, as the component for bias/LOD and the starting component of a
-         * gradient vector */
-
-        unsigned component_lo : 1;
+        /* 32-bit register, clear for half-register */
+        unsigned full : 1;
 
         /* Register select between r28/r29 */
         unsigned select : 1;
@@ -528,14 +525,8 @@ __attribute__((__packed__))
         /* For a half-register, selects the upper half */
         unsigned upper : 1;
 
-        /* Specifies a full-register, clear for a half-register. Mutually
-         * exclusive with upper. */
-        unsigned full : 1;
-
-        /* Higher half of component_lo. Always seen to be set for LOD/bias
-         * and clear for processed gradients, but I'm not sure if that's a
-         * hardware requirement. */
-        unsigned component_hi : 1;
+        /* Indexes into the register */
+        unsigned component : 2;
 
         /* Padding to make this 8-bit */
         unsigned zero : 3;

diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index 71625e8fd55b33a6098ff4d0ca0b7b47c74bea5a..d4112d09c256577708f3a44c10559e6f8e179ee0 100644 (file)
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -1650,10 +1650,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
                         midgard_tex_register_select sel = {
                                 .select = in_reg,
                                 .full = 1,
-
-                                /* w */
-                                .component_lo = 1,
-                                .component_hi = 1
+                                .component = COMPONENT_W,
                         };
 
                         uint8_t packed;