whoops test for sv.bc* matched accidentally, use explicit test

"svremap" and "svstate" instead

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 450f73f517eadff3a87b1435ee3cd9935731a339..c0ef32f988dd7f9a5d05e8fde845bc7c35f78341 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1224,7 +1224,7 @@ class ISACaller:
 
         # see if srcstep/dststep need skipping over masked-out predicate bits
         if (self.is_svp64_mode or ins_name == 'setvl' or
-           ins_name.startswith("sv")):
+           ins_name in ['svremap', 'svstate']):
             yield from self.svstate_pre_inc()
         if self.is_svp64_mode:
             pre = yield from self.update_new_svstate_steps()