rx.md: Add peepholes to match a register move followed by a comparison of the moved...

	* config/rx/rx.md: Add peepholes to match a register move followed
	by a comparison of the moved register.  Replace these with an
	addition of zero that does both actions in one instruction.

Co-Authored-By: Nick Clifton <nickc@redhat.com>
From-SVN: r173819

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 50b035615f8bc931348fc8490efc806f9ebd5b21..8ceeac30236e30f79c5e16e0519463f891e3797f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2011-05-17  Kazuhio Inaoka  <kazuhiro.inaoka.ud@renesas.com>
+           Nick Clifton  <nickc@redhat.com>
+
+       * config/rx/rx.md: Add peepholes to match a register move followed
+       by a comparison of the moved register.  Replace these with an
+       addition of zero that does both actions in one instruction.
+
 2011-05-17  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/48986

diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index a9cf50e21e34b264f218b37a65ddcf9e1a3cc8ab..fdbf2876a3e462dbff74979f7a29edf5a5a6608a 100644 (file)
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -904,6 +904,39 @@
    (set_attr "length"   "3,4,5,6,7,6")]
 )
 
+;; Peepholes to match:
+;;   (set (reg A) (reg B))
+;;   (set (CC) (compare:CC (reg A/reg B) (const_int 0)))
+;; and replace them with the addsi3_flags pattern, using an add
+;; of zero to copy the register and set the condition code bits.
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand")
+        (match_operand:SI 1 "register_operand"))
+   (set (reg:CC CC_REG)
+        (compare:CC (match_dup 0)
+                    (const_int 0)))]
+  ""
+  [(parallel [(set (match_dup 0)
+                  (plus:SI (match_dup 1) (const_int 0)))
+             (set (reg:CC_ZSC CC_REG)
+                  (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
+                                  (const_int 0)))])]
+)
+
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand")
+        (match_operand:SI 1 "register_operand"))
+   (set (reg:CC CC_REG)
+        (compare:CC (match_dup 1)
+                    (const_int 0)))]
+  ""
+  [(parallel [(set (match_dup 0)
+                  (plus:SI (match_dup 1) (const_int 0)))
+             (set (reg:CC_ZSC CC_REG)
+                  (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
+                                  (const_int 0)))])]
+)
+
 (define_expand "adddi3"
   [(set (match_operand:DI          0 "register_operand")
        (plus:DI (match_operand:DI 1 "register_operand")