vc4: Write the alignment of level width consistently in validation.

16 / cpp happens to be the same as utile_w on the only raster format
supported (4 bytes per pixel), but simulator/hw source code generally
talks in terms of utiles.

diff --git a/src/gallium/drivers/vc4/kernel/vc4_validate.c b/src/gallium/drivers/vc4/kernel/vc4_validate.c
index 0691a8d769ca4ad15bc46a2b5537a8f04c19854e..568b625e64b28513003749bd478ce2f88f207c10 100644 (file)
--- a/src/gallium/drivers/vc4/kernel/vc4_validate.c
+++ b/src/gallium/drivers/vc4/kernel/vc4_validate.c
@@ -164,7 +164,7 @@ check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
 
        switch (tiling_format) {
        case VC4_TILING_FORMAT_LINEAR:
-               aligned_width = roundup(width, 16 / cpp);
+               aligned_width = roundup(width, utile_w);
                aligned_height = height;
                break;
        case VC4_TILING_FORMAT_T:
@@ -951,7 +951,7 @@ reloc_tex(struct vc4_exec_info *exec,
                        aligned_height = roundup(level_height, utile_h);
                        break;
                default:
-                       aligned_width = roundup(level_width, 16 / cpp);
+                       aligned_width = roundup(level_width, utile_w);
                        aligned_height = level_height;
                        break;
                }