change riscv-isa-run to spike

diff --git a/configure b/configure
index da2d49c69525597ca65325a75e58dd91142e653c..7c02fa077a7d4e084233611d368fc56daff078a3 100755 (executable)
--- a/configure
+++ b/configure
@@ -559,7 +559,7 @@ MAKEFLAGS=
 
 # Identity of this package.
 PACKAGE_NAME='RISC-V ISA Simulator'
-PACKAGE_TARNAME='riscv-isa-run'
+PACKAGE_TARNAME='spike'
 PACKAGE_VERSION='?'
 PACKAGE_STRING='RISC-V ISA Simulator ?'
 PACKAGE_BUGREPORT='Andrew Waterman'
@@ -1256,7 +1256,7 @@ Fine tuning of the installation directories:
   --infodir=DIR           info documentation [DATAROOTDIR/info]
   --localedir=DIR         locale-dependent data [DATAROOTDIR/locale]
   --mandir=DIR            man documentation [DATAROOTDIR/man]
-  --docdir=DIR            documentation root [DATAROOTDIR/doc/riscv-isa-run]
+  --docdir=DIR            documentation root [DATAROOTDIR/doc/spike]
   --htmldir=DIR           html documentation [DOCDIR]
   --dvidir=DIR            dvi documentation [DOCDIR]
   --pdfdir=DIR            pdf documentation [DOCDIR]

diff --git a/configure.ac b/configure.ac
index 94d9980b2d8fd7d0e14b01e7c433e58ba96b9e0e..bb672e608938b04d38ec1fc41ba0ec2ebf6a4c1f 100644 (file)
--- a/configure.ac
+++ b/configure.ac
@@ -17,7 +17,7 @@
 
 m4_define( proj_name,         [RISC-V ISA Simulator])
 m4_define( proj_maintainer,   [Andrew Waterman])
-m4_define( proj_abbreviation, [riscv-isa-run])
+m4_define( proj_abbreviation, [spike])
 
 #-------------------------------------------------------------------------
 # Project version information

diff --git a/riscv/riscv-isa-run.cc b/riscv/riscv-isa-run.cc
deleted file mode 100644 (file)
index 142df33..0000000
--- a/riscv/riscv-isa-run.cc
+++ /dev/null
@@ -1,62 +0,0 @@
-// See LICENSE for license details.
-
-#include "sim.h"
-#include "htif.h"
-#include "cachesim.h"
-#include <fesvr/option_parser.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <getopt.h>
-#include <vector>
-#include <string>
-#include <memory>
-
-static void help()
-{
-  fprintf(stderr, "usage: riscv-isa-run [host options] <target program> [target options]\n");
-  fprintf(stderr, "Host Options:\n");
-  fprintf(stderr, "  -p <n>             Simulate <n> processors\n");
-  fprintf(stderr, "  -m <n>             Provide <n> MB of target memory\n");
-  fprintf(stderr, "  -d                 Interactive debug mode\n");
-  fprintf(stderr, "  -h                 Print this help message\n");
-  fprintf(stderr, "  -h                 Print this help message\n");
-  fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
-  fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
-  fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
-  exit(1);
-}
-
-int main(int argc, char** argv)
-{
-  bool debug = false;
-  size_t nprocs = 1;
-  size_t mem_mb = 0;
-  std::unique_ptr<icache_sim_t> ic;
-  std::unique_ptr<dcache_sim_t> dc;
-  std::unique_ptr<cache_sim_t> l2;
-
-  option_parser_t parser;
-  parser.help(&help);
-  parser.option('d', 0, 0, [&](const char* s){debug = true;});
-  parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
-  parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);});
-  parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
-  parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
-  parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
-
-  auto argv1 = parser.parse(argv);
-  if (!*argv1)
-    help();
-  std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
-  sim_t s(nprocs, mem_mb, htif_args);
-
-  if (ic && l2) ic->set_miss_handler(&*l2);
-  if (dc && l2) dc->set_miss_handler(&*l2);
-  for (size_t i = 0; i < nprocs; i++)
-  {
-    if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);
-    if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
-  }
-
-  s.run(debug);
-}

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index ea7b89870b82ff2aa8fc862f9dbe0c9d14f9437c..9a4ef57505c6f89cc7f10a00ddfcddcae3050f25 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -3,7 +3,7 @@ riscv_subproject_deps = \
        softfloat \
 
 riscv_install_prog_srcs = \
-       riscv-isa-run.cc \
+       spike.cc \
 
 riscv_hdrs := \
        htif.h \

diff --git a/riscv/spike.cc b/riscv/spike.cc
new file mode 100644 (file)
index 0000000..142df33
--- /dev/null
+++ b/riscv/spike.cc
@@ -0,0 +1,62 @@
+// See LICENSE for license details.
+
+#include "sim.h"
+#include "htif.h"
+#include "cachesim.h"
+#include <fesvr/option_parser.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <getopt.h>
+#include <vector>
+#include <string>
+#include <memory>
+
+static void help()
+{
+  fprintf(stderr, "usage: riscv-isa-run [host options] <target program> [target options]\n");
+  fprintf(stderr, "Host Options:\n");
+  fprintf(stderr, "  -p <n>             Simulate <n> processors\n");
+  fprintf(stderr, "  -m <n>             Provide <n> MB of target memory\n");
+  fprintf(stderr, "  -d                 Interactive debug mode\n");
+  fprintf(stderr, "  -h                 Print this help message\n");
+  fprintf(stderr, "  -h                 Print this help message\n");
+  fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
+  fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
+  fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
+  exit(1);
+}
+
+int main(int argc, char** argv)
+{
+  bool debug = false;
+  size_t nprocs = 1;
+  size_t mem_mb = 0;
+  std::unique_ptr<icache_sim_t> ic;
+  std::unique_ptr<dcache_sim_t> dc;
+  std::unique_ptr<cache_sim_t> l2;
+
+  option_parser_t parser;
+  parser.help(&help);
+  parser.option('d', 0, 0, [&](const char* s){debug = true;});
+  parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
+  parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);});
+  parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
+  parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
+  parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
+
+  auto argv1 = parser.parse(argv);
+  if (!*argv1)
+    help();
+  std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
+  sim_t s(nprocs, mem_mb, htif_args);
+
+  if (ic && l2) ic->set_miss_handler(&*l2);
+  if (dc && l2) dc->set_miss_handler(&*l2);
+  for (size_t i = 0; i < nprocs; i++)
+  {
+    if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);
+    if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
+  }
+
+  s.run(debug);
+}