Be more precise when connecting during ABC9 re-integration

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 21d207d33cc7b00eb8d0b35f89ca04bbe148666a..c3145dbe59416ed575927d73dd33e44ed17cb3a1 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -569,7 +569,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                        RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
                                        if (!a_bit.wire) {
                                                c->setPort("\\Y", module->addWire(NEW_ID));
-                                               module->connect(module->wires_[remap_name(y_bit.wire->name)], RTLIL::S1);
+                                               RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
+                                               log_assert(wire);
+                                               module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
                                        }
                                        else if (!lut_costs.empty() || !lut_file.empty()) {
                                                RTLIL::Cell* driving_lut = nullptr;